aboutsummaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
...
| * | | only one type of dff per slicePepijn de Vos2021-02-282-1/+9
|/ / /
* | | Merge pull request #603 from litghost/fix_trival_bad_swapgatecat2021-02-261-0/+12
|\ \ \ | |/ / |/| / | |/ Prevent trival misplacements in placer1.
| * Prevent trival misplacements in placer1.Keith Rothman2021-02-261-0/+12
|/ | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Merge pull request #602 from YosysHQ/gatecat/remove-unused-constrgatecat2021-02-262-187/+0
|\ | | | | Remove unused advanced timing constraint API
| * Remove unused advanced timing constraint APIgatecat2021-02-262-187/+0
|/ | | | | | | | | | | | | This API was simply an attractive nuisance as no code was ever developed to actually process timing constraints (other than clock constraints which use a different API). While I do want to consider basic false path support, among other things, in the near future; I plan for this to use a new API that doesn't add complexity to the BaseCtx/Context monstrosity and that is easier to use on the timing analysis side. Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #599 from litghost/allow_router2_to_use_preroutesgatecat2021-02-261-4/+54
|\ | | | | Allow router2 to use routed but not fixed arcs.
| * Allow router2 to use routed but not fixed arcs.Keith Rothman2021-02-251-4/+54
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #601 from YosysHQ/no-default-Werrorgatecat2021-02-261-1/+1
|\ \ | |/ |/| cmake: Don't enable any -Werror flags without opt-in
| * cmake: Don't enable any -Werror flags without opt-in.whitequark2021-02-261-1/+1
|/
* Merge pull request #598 from YosysHQ/gatecat/compiler-flagsgatecat2021-02-2520-62/+54
|\ | | | | Tighten up compiler flags
| * Fix compiler warnings introduced by -Wextragatecat2021-02-2519-59/+46
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * cmake: Enable -Wextra, and -Werror in some casesgatecat2021-02-252-4/+9
|/ | | | | | -Werror is not enabled by default, except on CI and for a few specific common traps, to avoid the inevitable breakages when new compiler versions add new diagnostics. Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #591 from litghost/add_constant_networkgatecat2021-02-2526-121/+1853
|\ | | | | Add constant network support to FPGA interchange arch
| * Fix assorted bugs in FPGA interchange.Keith Rothman2021-02-238-422/+626
| | | | | | | | | | | | | | | | | | | | Fixes: - Only use map constant pins during routing, and not during placement. - Unmapped cell ports have no BEL pins. - Fix SiteRouter congestion not taking into account initial expansion. - Fix psuedo-site pip output. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Finish dedicated interconnect implementation.Keith Rothman2021-02-233-139/+611
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Working FF example now that constant merging is done.Keith Rothman2021-02-236-8/+218
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Add initial logic for handling dedicated interconnect situations.Keith Rothman2021-02-2311-26/+587
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Move RapidWright git URI back to upstream.Keith Rothman2021-02-231-5/+1
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Remove some signedness warnings.Keith Rothman2021-02-233-11/+10
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Fix reference copy.Keith Rothman2021-02-231-6/+6
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Run "make clangformat".Keith Rothman2021-02-231-6/+8
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Initial working constant network support!Keith Rothman2021-02-234-14/+145
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Add constant network test case.Keith Rothman2021-02-235-0/+42
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Add tests to confirm constant routing import.Keith Rothman2021-02-233-9/+78
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Correct some bugs in the create_bba Makefile.Keith Rothman2021-02-231-3/+9
| | | | | | | | | | | | Also add debug_test target to debug archcheck. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Add initial constant network support to FPGA interchange arch.Keith Rothman2021-02-232-7/+47
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #597 from litghost/add_dynamic_bitarraygatecat2021-02-242-0/+79
|\ \ | | | | | | Add dynamic bitarray to common library.
| * | Bump tests submodule.Keith Rothman2021-02-241-0/+0
| | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * | Fix some bugs found in review.Keith Rothman2021-02-241-5/+2
| | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * | Add dynamic bitarray to common library.Keith Rothman2021-02-231-0/+82
| | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | | docs/archapi: Typo fixesgatecat2021-02-241-2/+2
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | Merge pull request #595 from litghost/const_cell_infogatecat2021-02-237-8/+8
|\ \ \ | | |/ | |/| Change CellInfo in getBelPinsForCellPin to be const.
| * | Update archapi.md with latest signature.Keith Rothman2021-02-231-1/+1
| | | | | | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * | Change CellInfo in getBelPinsForCellPin to be const.Keith Rothman2021-02-236-7/+7
| |/ | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #596 from litghost/make_clang_formatgatecat2021-02-232-11/+16
|\ \ | |/ |/| Run "make clangformat" to fix formatting in new Bits library.
| * Run "make clangformat" to fix new Bits library.Keith Rothman2021-02-232-11/+16
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #594 from YosysHQ/gatecat/heap-tidyinggatecat2021-02-236-41/+88
|\ \ | |/ |/| Tidying up HeAP
| * Refactor some common code to CellInfo methodsgatecat2021-02-236-38/+43
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * HeAP: Document legalise_placement_strict bettergatecat2021-02-231-3/+45
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: Fix getPipDelay returning negative after refactorgatecat2021-02-231-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* pyconsole: Avoid lockup when reading from stdingatecat2021-02-221-0/+2
| | | | | | | | Create an empty temporary file for stdin; so reads fail rather than locking up (otherwise doing help() would be enough to completely lock up the GUI). Signed-off-by: gatecat <gatecat@ds0.me>
* Demote the 'no clocks' warning to info and make clearergatecat2021-02-201-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #592 from YosysHQ/gatecat/rework-delaygatecat2021-02-2035-502/+307
|\ | | | | Replace DelayInfo with DelayPair and DelayQuad
| * Update generic.mdgatecat2021-02-201-4/+4
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * python: Bindings for DelayPair and DelayQuadgatecat2021-02-191-0/+25
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-1933-498/+243
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This replaces the arch-specific DelayInfo structure with new DelayPair (min/max only) and DelayQuad (min/max for both rise and fall) structures that form part of common code. This further reduces the amount of arch-specific code; and also provides useful data structures for timing analysis which will need to delay with pairs/quads of delays as it is improved. While there may be a small performance cost to arches that didn't separate the rise/fall cases (arches that aren't currently separating the min/max cases just need to be fixed...) in DelayInfo, my expectation is that inlining will mean this doesn't make much difference. Signed-off-by: gatecat <gatecat@ds0.me>
| * Add DelayPair and DelayQuad structuresgatecat2021-02-191-0/+35
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | clangformatgatecat2021-02-191-1/+2
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #576 from litghost/add_cell_bel_pin_mappinggatecat2021-02-1928-86/+2251
|\ | | | | Complete FPGA interchange Arch to the point where it can route a wire
| * Fix sign mismatch.Keith Rothman2021-02-182-2/+2
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-12 20:03:36 +0000