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* mistral: Disable global buffers that are currently brokengatecat2021-05-151-0/+2
* router2: Reduce verbosity when debugginggatecat2021-05-151-0/+2
* mistral: Compensate for EF_SEL mirroring in validity checkgatecat2021-05-151-2/+2
* mistral: Fix EF_SEL and BTO_DISgatecat2021-05-152-4/+5
* mistral: PKREG bits appear to be mirrored within a half?gatecat2021-05-151-2/+3
* mistral: Debugging flipflopsgatecat2021-05-151-3/+4
* mistral: Trim SDATA if SLOAD is lowgatecat2021-05-151-0/+9
* mistral: FF&CLKBUF fixes, part 1gatecat2021-05-152-1/+10
* mistral: First pass at FF and CLKBUF bitgengatecat2021-05-152-18/+115
* mistral: Account for TD input count limitgatecat2021-05-154-9/+128
* msitral: Fix pip iterator Python bindingsgatecat2021-05-151-2/+2
* mistral: Implement PIP locations, toogatecat2021-05-151-1/+1
* mistral: Implement bounding boxes for router2gatecat2021-05-152-1/+15
* mistral: Debugging carry chain issuesgatecat2021-05-152-13/+34
* mistral: Adding FF control set reservationgatecat2021-05-153-58/+148
* mistral: Carry fixesgatecat2021-05-152-3/+16
* mistral: Carry debugginggatecat2021-05-153-41/+11
* mistral: Write arith mode to bitstream (not yet functional)gatecat2021-05-152-2/+18
* mistral: First pass at carry packinggatecat2021-05-154-8/+82
* mistral: FF validity checking fixesgatecat2021-05-151-7/+13
* mistral: Fix constant trimminggatecat2021-05-152-1/+2
* mistral: Write LUT initsgatecat2021-05-152-1/+72
* mistral: Add some IO configurationgatecat2021-05-151-0/+30
* mistral: Setting some more boilerplate bitsgatecat2021-05-153-1/+118
* mistral: Add stub RBF generationgatecat2021-05-154-9/+108
* mistral: Rename clock buffer primitivegatecat2021-05-152-2/+3
* mistral: Python and GUI stubgatecat2021-05-156-0/+350
* mistral: Implement some misc. thingsgatecat2021-05-154-10/+78
* mistral: Some preps for generating bitstreamsgatecat2021-05-154-28/+131
* mistral: Adding a function for computing ALM LUT masksgatecat2021-05-152-0/+90
* mistral: Add IO packinggatecat2021-05-155-8/+135
* mistral: Add a basic QSF parsergatecat2021-05-154-1/+295
* mistral: Add some packing logic based on nexusgatecat2021-05-154-3/+202
* mistral: Working on FF validity checkinggatecat2021-05-152-1/+117
* mistral: Add the 'pin style' stuff based on Nexusgatecat2021-05-152-0/+112
* mistral: Working on ALM input assignmentgatecat2021-05-152-2/+118
* mistral: Add stub pack/place/route functionsgatecat2021-05-155-5/+143
* mistral: Renamed arch from cyclonevgatecat2021-05-159-4/+4
* cyclonev: Rebase updategatecat2021-05-151-1/+3
* cyclonev: More validity checking thoughtsgatecat2021-05-155-7/+49
* cyclonev: Add validity check and IO belsgatecat2021-05-155-9/+92
* cyclonev: First (untested) pass at ALM validity checkinggatecat2021-05-152-40/+135
* cyclonev: More preparations for validity checkinggatecat2021-05-155-7/+159
* cyclonev: Preparations for validity checkinggatecat2021-05-152-0/+37
* cyclonev: Fix some archcheck failsgatecat2021-05-153-4/+6
* cyclonev: Rework belsgatecat2021-05-153-97/+76
* cyclonev: Outline LAB structuregatecat2021-05-154-4/+207
* cyclonev: Outline functions for creating bels/wires/pipsgatecat2021-05-152-3/+104
* archcheck: Use old connectivity check for CycloneVgatecat2021-05-151-1/+29
* cyclonev: Add routing graphgatecat2021-05-152-4/+73
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