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* ecp5: Copy REGMODE in PDP mode to both A and B portsgatecat2021-08-021-1/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #787 from YosysHQ/gatecat/reportgatecat2021-07-309-1/+136
|\ | | | | Add JSON utilisation and timing report
| * common: Add JSON timing and utilisation reportgatecat2021-07-294-0/+105
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * basectx: Add a field to store timing resultsgatecat2021-07-295-1/+31
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #788 from YosysHQ/gatecat/router2-ice40gatecat2021-07-301-1/+9
|\ \ | |/ |/| router2: Mark the destination as visited during backwards routing
| * router2: Mark dest as visited during backwards routinggatecat2021-07-301-0/+4
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * router2: Improve debugability of pip conflictsgatecat2021-07-291-1/+5
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #785 from YosysHQ/gatecat/nexus2glb2fabricgatecat2021-07-292-2/+37
|\ | | | | nexus: Fix routeing of global clocks that also drive fabric
| * nexus: Fix routeing of global clocks that also drive fabricgatecat2021-07-282-2/+37
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #784 from YosysHQ/gatecat/nexus-ddrgatecat2021-07-285-4/+154
|\ | | | | nexus: Basic IDDRX1/ODDRX1 support
| * nexus: Basic packer and FASM support for I/ODDRgatecat2021-07-284-2/+124
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * nexus: Add IOLOGIC pins datagatecat2021-07-283-2/+30
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #783 from YosysHQ/gatecat/router2-crit-updategatecat2021-07-281-1/+43
|\ \ | |/ |/| router2: Update route delays even when routes are congested
| * router2: Update route delays even when routes are congestedgatecat2021-07-281-1/+43
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* timing: Allow overriding of route delaysgatecat2021-07-282-3/+10
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #780 from YosysHQ/gatecat/fix-io-invgatecat2021-07-261-13/+32
|\ | | | | interchange: Search backwards for IO macro placements, too
| * interchange: Search backwards for IO macro placements, toogatecat2021-07-261-13/+32
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #779 from YosysHQ/gatecat/ic-import-fixgatecat2021-07-261-5/+0
|\ \ | |/ |/| interchange: Don't attempt to import instances as modules
| * interchange: Don't attempt to import instances as modulesgatecat2021-07-261-5/+0
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #775 from YosysHQ/gatecat/fix-io-checksgatecat2021-07-261-6/+16
|\ | | | | interchange: Check IO validity after all are placed
| * interchange: Check IO validity after all are placedgatecat2021-07-231-6/+16
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #777 from YosysHQ/gatecat/gui-fixesgatecat2021-07-255-5/+20
|\ \ | |/ |/| gui: Add about box and fix some small typos
| * gui: Fix some typosgatecat2021-07-252-5/+5
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * gui: Implement about dialoggatecat2021-07-254-0/+15
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #757 from antmicro/lut-mapping-cachegatecat2021-07-228-74/+510
|\ | | | | interchange: Add caching of site LUT mapping solution
| * Added an option to disable the LUT mapping cacheMaciej Kurc2021-07-225-8/+16
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Added more code comments, formatted the codeMaciej Kurc2021-07-226-123/+124
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Added computing and reporting LUT mapping cache sizeMaciej Kurc2021-07-162-0/+37
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Fixed assertion typosMaciej Kurc2021-07-161-2/+2
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Migrated C arrays to std::array containers.Maciej Kurc2021-07-162-9/+31
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * LUT mapping ceche optimizations 2Maciej Kurc2021-07-163-93/+17
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * LUT mapping cache optimizations 1Maciej Kurc2021-07-162-32/+48
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
| * Working site LUT mapping cacheMaciej Kurc2021-07-167-42/+470
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* | Merge pull request #772 from antmicro/xdc_parsegatecat2021-07-211-0/+7
|\ \ | | | | | | [Interchange] Add dummy function to parse creat_clock in XDC files
| * | Add dummy function to parse creat_clock in XDC filesMaciej Dudek2021-07-211-0/+7
|/ / | | | | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
* | Merge pull request #768 from YosysHQ/gatecat/fix-gui-errorgatecat2021-07-212-11/+62
|\ \ | | | | | | gui: Improve Fatal Error message
| * | gui: Improve Fatal Error messagegatecat2021-07-202-11/+62
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | clangformatgatecat2021-07-211-1/+1
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | Merge pull request #770 from YosysHQ/gatecat/empty-idstringlistgatecat2021-07-201-1/+1
|\ \ \ | | | | | | | | Fix definition of an empty IdStringList
| * | | Fix definition of an empty IdStringListgatecat2021-07-201-1/+1
| |/ / | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | Merge pull request #771 from YosysHQ/gatecat/ice40-ip-no-busaddr74gatecat2021-07-201-3/+4
|\ \ \ | |/ / |/| | ice40: Use default value when IP is missing BUS_ADDR74 parameter
| * | ice40: Use default value when IP is missing BUS_ADDR74 parametergatecat2021-07-201-3/+4
|/ / | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #767 from YosysHQ/gatecat/ic-pref-constgatecat2021-07-201-1/+10
|\ \ | | | | | | interchange: Fix preferred constant handling when canInvert
| * | interchange: Fix preferred constant handling when canInvertgatecat2021-07-201-1/+10
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | Merge pull request #766 from pepijndevos/pythongatecat2021-07-172-4/+2
|\ \ \ | | | | | | | | Remove python path from gowin target
| * | | remove generic leftover in gowinPepijn de Vos2021-07-171-2/+2
| | | |
| * | | remove generic leftover in gowinPepijn de Vos2021-07-171-2/+0
|/ / /
* | | Merge pull request #764 from acomodi/fix-pseudo-pipsgatecat2021-07-151-8/+18
|\ \ \ | |/ / |/| | interchange: disallow pseudo-pip on same nets if tile has luts
| * | interchange: disallow pseudo-pip on same nets if tile has lutsAlessandro Comodi2021-07-151-8/+18
|/ / | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* | Merge pull request #762 from antmicro/testarch_timinggatecat2021-07-142-2/+2
|\ \ | | | | | | [interchange] Update chipdb and python-fpga-interchange versions
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