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Port nextpnr-{ice40,ecp5} to WASI.
whitequark
2020-05-23
8
-20
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+108
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Merge pull request #440 from YosysHQ/lattice-fixes
David Shah
2020-05-18
3
-0
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+28
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ecp5: Disconnect dedicated DCU inputs if connected to constants
David Shah
2020-05-14
1
-0
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+12
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ecp5: Improve global routing robustness
David Shah
2020-05-14
1
-0
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+11
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ecp5: Don't promote VCC/GND to globals even if connected to clock port
David Shah
2020-05-14
1
-0
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+2
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lpf: Support // comments
David Shah
2020-05-14
1
-0
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+3
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clangformat
David Shah
2020-05-16
2
-4
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+4
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Merge pull request #442 from nategraff-sifive/fix-unsupported-spelling
David Shah
2020-05-14
3
-10
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+10
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Fix spelling of 'unsupported'
Nathaniel Graff
2020-05-13
3
-10
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+10
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Merge pull request #441 from YosysHQ/eddie/fix_topo
Miodrag Milanović
2020-05-14
1
-16
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+16
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Fix embarassing use of topographical when meaning topological
Eddie Hung
2020-05-14
1
-16
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+16
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Merge pull request #439 from edbordin/master
Miodrag Milanović
2020-05-14
1
-4
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+6
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minor patch for MinGW build
Ed Bordin
2020-05-14
1
-4
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+6
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Merge pull request #437 from miek/lvcmos33d-drive
David Shah
2020-05-12
1
-0
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+19
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ecp5: Allow setting drive strength for LVCMOS33D IOs
Mike Walters
2020-05-12
1
-0
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+19
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Add missing --top option
David Shah
2020-05-09
1
-0
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+5
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Merge branch 'rschlaikjer-rschlaikjer-mult18x18-register-timings'
David Shah
2020-05-01
3
-6
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+125
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ecp5: MULT18X18D timing fixes
David Shah
2020-05-01
1
-10
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+26
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No cell delay for clocked MULT18X18D
Ross Schlaikjer
2020-04-30
1
-0
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+2
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Further condense
Ross Schlaikjer
2020-04-29
1
-11
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+10
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Dedupe clock error check
Ross Schlaikjer
2020-04-29
1
-12
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+13
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Issue warning for mixed-mode inputs
Ross Schlaikjer
2020-04-29
3
-40
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+46
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Handle register timing case
Ross Schlaikjer
2020-04-29
1
-6
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+58
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Use registered port class on mult18x18
Ross Schlaikjer
2020-04-29
1
-3
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+5
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Alter MULT18X18D timing db based on register config
Ross Schlaikjer
2020-04-28
3
-2
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+43
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Merge pull request #433 from YosysHQ/dave/pyfixes
David Shah
2020-04-24
2
-4
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+17
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python: Also convert regular map keys to string
David Shah
2020-04-24
1
-1
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+3
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python: Improve general robustness during autocomplete
David Shah
2020-04-24
1
-0
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+4
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python: Escape strings for autocomplete
David Shah
2020-04-24
1
-2
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+8
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python: Wrap map IdString key when accessed by index
David Shah
2020-04-24
1
-1
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+2
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Merge pull request #432 from smunaut/fix_disconnect
David Shah
2020-04-24
1
-0
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+1
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design_utils: Set port.net to null when disconnecting
Sylvain Munaut
2020-04-24
1
-0
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+1
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Merge pull request #428 from mmicko/master
Miodrag Milanović
2020-04-20
1
-2
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+2
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old boost support
Miodrag Milanovic
2020-04-20
1
-2
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+2
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ecp5: Fix CSDECODE bitgen
David Shah
2020-04-15
1
-0
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+3
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Merge pull request #426 from YosysHQ/dave/fix-pll2eclk
David Shah
2020-04-15
1
-1
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+80
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ecp5: Use dedicated routing for ECLKs where possible
David Shah
2020-04-14
1
-1
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+80
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Add TRELLIS_PROGRAM_PREFIX
Miodrag Milanovic
2020-04-11
1
-4
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+6
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Merge pull request #424 from mmicko/program_prefix
David Shah
2020-04-10
1
-10
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+12
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Support custom PROGRAM_PREFIX
Miodrag Milanovic
2020-04-10
1
-10
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+12
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ecp5: Fix routing bitgen for non-SERDES 'VCIB' tiles
David Shah
2020-04-10
1
-3
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+12
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ecp5: Make hysteresis default-on for LVCMOS33 bidir as well as input
David Shah
2020-04-09
1
-9
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+7
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Merge pull request #423 from rschlaikjer/rschlaikjer-regmode-timing-database
David Shah
2020-04-07
3
-4
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+33
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No need to fetch context
Ross Schlaikjer
2020-04-07
1
-3
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+2
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Change assert to error
Ross Schlaikjer
2020-04-07
1
-2
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+5
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Rearrange bool algebra
Ross Schlaikjer
2020-04-07
1
-2
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+2
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Actually just move all the logic to ArchInfo
Ross Schlaikjer
2020-04-07
3
-19
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+23
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Extract regmode configuration to ArchInfo
Ross Schlaikjer
2020-04-07
3
-8
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+16
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Change timing database lookup based on REGMODE value
Ross Schlaikjer
2020-04-07
1
-4
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+19
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Merge pull request #419 from garytwong/handle-opendrain
David Shah
2020-04-07
1
-0
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+3
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