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| * clang-formatSergiusz Bazanski2018-07-244-67/+74
| * ice40: A slightly nicer way to do this.Sergiusz Bazanski2018-07-241-46/+31
| * ice40: Move spliceLUT back to pack.ccSergiusz Bazanski2018-07-243-56/+53
| * ice40: Prevent placement of SB_IOs in IO blocks used by PLL outputsSergiusz Bazanski2018-07-241-0/+24
| * ice40: Refactor PLL/LOCK LUT splicing out into Arch::Sergiusz Bazanski2018-07-244-74/+59
| * ice40: Emit feed-through LUTs for PLL/LOCKSergiusz Bazanski2018-07-243-5/+159
| * ice40: Fail early on SB_PLL40_*_PAD cellsSergiusz Bazanski2018-07-242-0/+14
| * ice40: Implement emitting PLLsSergiusz Bazanski2018-07-2412-17/+275
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* make update of tree for nets and cells partialMiodrag Milanovic2018-07-232-26/+56
* ecp5: Add some more PIO helper functionsDavid Shah2018-07-232-0/+42
* ecp5: Helper functions for I/O placement and checkingDavid Shah2018-07-233-0/+324
* Proper highlight/selected cleanup on context re-initMiodrag Milanovic2018-07-232-0/+4
* write frequency infoMiodrag Milanovic2018-07-231-0/+1
* always assign budget before placingMiodrag Milanovic2018-07-231-2/+2
* Add Context::archcheck() and "nextpnr-ice40 --test"Clifford Wolf2018-07-235-45/+208
* Remove getBelsByType() APIClifford Wolf2018-07-234-40/+0
* clangformatDavid Shah2018-07-232-4/+5
* ecp5: Add Add getGridDimX(), getGridDimY(), getTileDimZ()David Shah2018-07-231-0/+5
* clangformatClifford Wolf2018-07-232-20/+26
* Add fallback to estimateDelay() in getNetinfoRouteDelay()Clifford Wolf2018-07-231-1/+6
* Add getGridDimX(), getGridDimY(), getTileDimZ() APIClifford Wolf2018-07-233-1/+31
* ecp5: Implement new Grid APIsDavid Shah2018-07-232-0/+50
* ecp5: Remove obsolete db entries, add Bel z-positionDavid Shah2018-07-232-19/+2
* Bugfix in iCE40 chipdb.pyClifford Wolf2018-07-231-3/+0
* Added Bel port info to GUIMiodrag Milanovic2018-07-221-0/+8
* Move to new API and remove deprecatedMiodrag Milanovic2018-07-226-94/+40
* Move to new apiMiodrag Milanovic2018-07-221-12/+3
* ecp5: Adding new Bel pin APIDavid Shah2018-07-223-3/+63
* ecp5: Fix regression following router updateDavid Shah2018-07-222-2/+2
* Add Arch::getBelPins() to generic and iCE40 archsClifford Wolf2018-07-224-0/+25
* Add Arch::getBelPinType() and Arch::getWireBelPins() in iCE40 archClifford Wolf2018-07-223-4/+57
* Add Arch::getBelPinType() and Arch::getWireBelPins() in generic archClifford Wolf2018-07-222-2/+12
* Rename getWireBelPin to getBelPinWireClifford Wolf2018-07-2212-26/+26
* Move common patterns from router1 to Context APIClifford Wolf2018-07-223-150/+124
* clangformatClifford Wolf2018-07-225-39/+30
* QTimer::start(std::chrono::duration -> int)Sergiusz Bazanski2018-07-212-3/+3
* Merge branch 'q3k/lock-2-electric-boogaloo' into 'master'Clifford Wolf2018-07-217-161/+397
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| * Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/lock-2-elec...Sergiusz Bazanski2018-07-2122-682/+1466
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| * | Re-enable drawing Pips.Sergiusz Bazanski2018-07-201-3/+3
| * | Use UI lock for yieldingSergiusz Bazanski2018-07-204-14/+40
| * | clang-formatSergiusz Bazanski2018-07-201-1/+1
| * | Nuke IdStringDBSergiusz Bazanski2018-07-205-50/+41
| * | Remove dead code.Sergiusz Bazanski2018-07-201-2/+0
| * | clang-format and uncomment debugSergiusz Bazanski2018-07-204-45/+39
| * | Move pthread yield hack into BaseCtxSergiusz Bazanski2018-07-203-10/+14
| * | Mix-in Deterministic RNG at Context instead of BaseCtxSergiusz Bazanski2018-07-201-2/+2
| * | Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/lock-2-elec...Sergiusz Bazanski2018-07-2048-825/+754
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| * | | Refactor renderer threadSergiusz Bazanski2018-07-202-27/+64
| * | | WIP.Serge Bazanski2018-07-177-96/+227
| * | | Add basic external locking, lock from P&RSerge Bazanski2018-07-173-0/+40
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