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* interchange: ci: add RW patch for missing cell bel mapsAlessandro Comodi2021-06-111-0/+3
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: clusters: always get cell bel map and add assertsAlessandro Comodi2021-06-111-23/+13
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: ci: update python-interchange tagAlessandro Comodi2021-06-111-1/+1
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: run clang formatterAlessandro Comodi2021-06-112-22/+18
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: clusters: adjust commentsAlessandro Comodi2021-06-112-11/+16
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: increase chipinfo versionAlessandro Comodi2021-06-111-1/+1
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: tests: counter: emit carries for xc7Alessandro Comodi2021-06-112-4/+6
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* interchange: add support for generating BEL clustersAlessandro Comodi2021-06-119-24/+713
| | | | | | | | Clustering greatly helps the placer to identify and pack together specific cells at the same site (e.g. LUT+FF), or cells that are chained through dedicated interconnections (e.g. CARRY CHAINS) Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* Merge branch 'test_framework'gatecat2021-06-112-0/+3
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| * fpga_interchange: Add site router testsTomasz Michalak2021-06-111-0/+3
| | | | | | | | Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
| * tests: fpga_interchange: Update module to use site router test frameworkTomasz Michalak2021-06-111-0/+0
|/ | | | Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
* ecp5: Add missing clock edge assignmentsgatecat2021-06-101-0/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: Fix LRAM x coordgatecat2021-06-101-0/+2
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* Merge pull request #723 from YosysHQ/gatecat/fix-722gatecat2021-06-083-11/+16
|\ | | | | gui: Don't destroy context when loading JSON
| * gui: Don't destroy context when loading JSONgatecat2021-06-073-11/+16
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | ecp5: Don't attempt to promote undriven nets to globalsgatecat2021-06-071-1/+2
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Fix include path in GUI cmake, toogatecat2021-06-071-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #721 from YosysHQ/gatecat/mistral-cmakegatecat2021-06-057-17/+7
|\ | | | | Updates for latest libmistral
| * ci: Bump mistral versiongatecat2021-06-052-6/+2
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * mistral: Remove mistral root argumentgatecat2021-06-043-7/+1
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * mistral: Build libmistral as a cmake subdirgatecat2021-06-042-4/+4
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #718 from YosysHQ/gatecat/hashlibgatecat2021-06-03137-1658/+2152
|\ | | | | Moving from unordered_{map, set} to hashlib
| * Remove redundant code after hashlib movegatecat2021-06-0220-498/+14
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * Use hashlib in frontend, where possiblegatecat2021-06-021-6/+6
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * Use hashlib in most remaining codegatecat2021-06-0220-58/+53
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * Using hashlib in timinggatecat2021-06-022-82/+26
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * Using hashlib in archesgatecat2021-06-0266-549/+358
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * Use hashlib in routersgatecat2021-06-024-41/+37
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * Bump tests submodulegatecat2021-06-021-0/+0
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * Use hashlib in placersgatecat2021-06-027-52/+43
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * Use hashlib for core netlist structuresgatecat2021-06-0249-368/+383
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * Add hash() member functionsgatecat2021-06-029-7/+51
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * common: Import hashlib from Yosysgatecat2021-06-022-0/+1184
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #719 from YosysHQ/gatecat/mistral-llvmgatecat2021-06-023-4/+4
|\ | | | | mistral: Fix nextpnr build with LLVM
| * mistral: Fix nextpnr build with LLVMgatecat2021-06-023-4/+4
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* clangformatgatecat2021-06-011-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #717 from YosysHQ/gatecat/timing-memory-fixgatecat2021-06-011-1/+1
|\ | | | | timing: Fix use of uninitialised value
| * timing: Fix use of uninitialised valuegatecat2021-06-011-1/+1
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #715 from YosysHQ/gatecat/ic-lifcl40gatecat2021-06-0112-4/+85
|\ \ | |/ |/| interchange: Add LIFCL-40 EVN tests
| * interchange: Add LIFCL-40 EVN testsgatecat2021-06-0112-4/+85
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Fixed warnings in QtPropertyBrowser componentMiodrag Milanovic2021-05-312-2/+0
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* Fix hidpi, fixes #167, fixes #275, fixes #425Miodrag Milanovic2021-05-312-3/+10
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* Merge pull request #714 from YosysHQ/gatecat/mistral-dis-compressgatecat2021-05-302-1/+9
|\ | | | | mistral: Make RBF compression optional
| * mistral: Make RBF compression optionalgatecat2021-05-302-1/+9
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #713 from YosysHQ/gatecat/version-bumpgatecat2021-05-272-1/+1
|\ | | | | interchange: Bump versions
| * interchange: Bump versionsgatecat2021-05-272-1/+1
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #686 from YosysHQ/gatecat/interchange-macrogatecat2021-05-2114-4/+414
|\ | | | | interchange: Add macro expansion
| * interchange: Bump versionsgatecat2021-05-212-1/+1
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * interchange: Add macro parameter mappinggatecat2021-05-212-3/+53
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * interchange: Don't error out on missing cell portsgatecat2021-05-212-2/+3
| | | | | | | | | | | | | | This is required for LUTRAM support, as the upper address bits of RAMD64E etc are missing for shallower primitives. Signed-off-by: gatecat <gatecat@ds0.me>
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-31 18:46:52 +0000