Commit message (Collapse) | Author | Age | Files | Lines | |
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* | interchange: ci: add RW patch for missing cell bel maps | Alessandro Comodi | 2021-06-11 | 1 | -0/+3 |
| | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
* | interchange: clusters: always get cell bel map and add asserts | Alessandro Comodi | 2021-06-11 | 1 | -23/+13 |
| | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
* | interchange: ci: update python-interchange tag | Alessandro Comodi | 2021-06-11 | 1 | -1/+1 |
| | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
* | interchange: run clang formatter | Alessandro Comodi | 2021-06-11 | 2 | -22/+18 |
| | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
* | interchange: clusters: adjust comments | Alessandro Comodi | 2021-06-11 | 2 | -11/+16 |
| | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
* | interchange: increase chipinfo version | Alessandro Comodi | 2021-06-11 | 1 | -1/+1 |
| | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
* | interchange: tests: counter: emit carries for xc7 | Alessandro Comodi | 2021-06-11 | 2 | -4/+6 |
| | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
* | interchange: add support for generating BEL clusters | Alessandro Comodi | 2021-06-11 | 9 | -24/+713 |
| | | | | | | | | Clustering greatly helps the placer to identify and pack together specific cells at the same site (e.g. LUT+FF), or cells that are chained through dedicated interconnections (e.g. CARRY CHAINS) Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
* | Merge branch 'test_framework' | gatecat | 2021-06-11 | 2 | -0/+3 |
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| * | fpga_interchange: Add site router tests | Tomasz Michalak | 2021-06-11 | 1 | -0/+3 |
| | | | | | | | | Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com> | ||||
| * | tests: fpga_interchange: Update module to use site router test framework | Tomasz Michalak | 2021-06-11 | 1 | -0/+0 |
|/ | | | | Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com> | ||||
* | ecp5: Add missing clock edge assignments | gatecat | 2021-06-10 | 1 | -0/+2 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | nexus: Fix LRAM x coord | gatecat | 2021-06-10 | 1 | -0/+2 |
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* | Merge pull request #723 from YosysHQ/gatecat/fix-722 | gatecat | 2021-06-08 | 3 | -11/+16 |
|\ | | | | | gui: Don't destroy context when loading JSON | ||||
| * | gui: Don't destroy context when loading JSON | gatecat | 2021-06-07 | 3 | -11/+16 |
| | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | | ecp5: Don't attempt to promote undriven nets to globals | gatecat | 2021-06-07 | 1 | -1/+2 |
|/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | mistral: Fix include path in GUI cmake, too | gatecat | 2021-06-07 | 1 | -1/+1 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Merge pull request #721 from YosysHQ/gatecat/mistral-cmake | gatecat | 2021-06-05 | 7 | -17/+7 |
|\ | | | | | Updates for latest libmistral | ||||
| * | ci: Bump mistral version | gatecat | 2021-06-05 | 2 | -6/+2 |
| | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | mistral: Remove mistral root argument | gatecat | 2021-06-04 | 3 | -7/+1 |
| | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | mistral: Build libmistral as a cmake subdir | gatecat | 2021-06-04 | 2 | -4/+4 |
|/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Merge pull request #718 from YosysHQ/gatecat/hashlib | gatecat | 2021-06-03 | 137 | -1658/+2152 |
|\ | | | | | Moving from unordered_{map, set} to hashlib | ||||
| * | Remove redundant code after hashlib move | gatecat | 2021-06-02 | 20 | -498/+14 |
| | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Use hashlib in frontend, where possible | gatecat | 2021-06-02 | 1 | -6/+6 |
| | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Use hashlib in most remaining code | gatecat | 2021-06-02 | 20 | -58/+53 |
| | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Using hashlib in timing | gatecat | 2021-06-02 | 2 | -82/+26 |
| | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Using hashlib in arches | gatecat | 2021-06-02 | 66 | -549/+358 |
| | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Use hashlib in routers | gatecat | 2021-06-02 | 4 | -41/+37 |
| | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Bump tests submodule | gatecat | 2021-06-02 | 1 | -0/+0 |
| | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Use hashlib in placers | gatecat | 2021-06-02 | 7 | -52/+43 |
| | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Use hashlib for core netlist structures | gatecat | 2021-06-02 | 49 | -368/+383 |
| | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Add hash() member functions | gatecat | 2021-06-02 | 9 | -7/+51 |
| | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | common: Import hashlib from Yosys | gatecat | 2021-06-02 | 2 | -0/+1184 |
|/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Merge pull request #719 from YosysHQ/gatecat/mistral-llvm | gatecat | 2021-06-02 | 3 | -4/+4 |
|\ | | | | | mistral: Fix nextpnr build with LLVM | ||||
| * | mistral: Fix nextpnr build with LLVM | gatecat | 2021-06-02 | 3 | -4/+4 |
|/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | clangformat | gatecat | 2021-06-01 | 1 | -1/+1 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Merge pull request #717 from YosysHQ/gatecat/timing-memory-fix | gatecat | 2021-06-01 | 1 | -1/+1 |
|\ | | | | | timing: Fix use of uninitialised value | ||||
| * | timing: Fix use of uninitialised value | gatecat | 2021-06-01 | 1 | -1/+1 |
| | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | | Merge pull request #715 from YosysHQ/gatecat/ic-lifcl40 | gatecat | 2021-06-01 | 12 | -4/+85 |
|\ \ | |/ |/| | interchange: Add LIFCL-40 EVN tests | ||||
| * | interchange: Add LIFCL-40 EVN tests | gatecat | 2021-06-01 | 12 | -4/+85 |
|/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Fixed warnings in QtPropertyBrowser component | Miodrag Milanovic | 2021-05-31 | 2 | -2/+0 |
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* | Fix hidpi, fixes #167, fixes #275, fixes #425 | Miodrag Milanovic | 2021-05-31 | 2 | -3/+10 |
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* | Merge pull request #714 from YosysHQ/gatecat/mistral-dis-compress | gatecat | 2021-05-30 | 2 | -1/+9 |
|\ | | | | | mistral: Make RBF compression optional | ||||
| * | mistral: Make RBF compression optional | gatecat | 2021-05-30 | 2 | -1/+9 |
|/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Merge pull request #713 from YosysHQ/gatecat/version-bump | gatecat | 2021-05-27 | 2 | -1/+1 |
|\ | | | | | interchange: Bump versions | ||||
| * | interchange: Bump versions | gatecat | 2021-05-27 | 2 | -1/+1 |
|/ | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Merge pull request #686 from YosysHQ/gatecat/interchange-macro | gatecat | 2021-05-21 | 14 | -4/+414 |
|\ | | | | | interchange: Add macro expansion | ||||
| * | interchange: Bump versions | gatecat | 2021-05-21 | 2 | -1/+1 |
| | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | interchange: Add macro parameter mapping | gatecat | 2021-05-21 | 2 | -3/+53 |
| | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | interchange: Don't error out on missing cell ports | gatecat | 2021-05-21 | 2 | -2/+3 |
| | | | | | | | | | | | | | | This is required for LUTRAM support, as the upper address bits of RAMD64E etc are missing for shallower primitives. Signed-off-by: gatecat <gatecat@ds0.me> |