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* Merge pull request #1090 from rowanG077/ecp5-propagate-dcsc-clk-ctmyrtle2023-02-132-14/+160
|\ | | | | ecp5: Propagate clock constraints through DCSC
| * streamline constant_net detectionrowanG0772023-02-062-4/+8
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| * ecp5: DSCS clock propagation if modesel is 0 constantrowanG0772023-02-061-52/+99
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| * ecp5: Propagate clock constraints through DSCSrowanG0772023-02-011-12/+107
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* | Merge pull request #1097 from YosysHQ/gatecat/fab-bram-fixmyrtle2023-02-102-6/+25
|\ \ | | | | | | fabulous: Improve names for BRAM bels
| * | fabulous: Improve names for BRAM belsgatecat2023-02-102-6/+25
|/ / | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #1096 from YosysHQ/gatecat/ecp5-ioce-fixmyrtle2023-02-101-2/+8
|\ \ | | | | | | ecp5: Handle the case where both CE are the same constant
| * | ecp5: Handle the case where both CE are the same constantgatecat2023-02-091-2/+8
|/ / | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #1094 from uis246/mastermyrtle2023-02-072-0/+21
|\ \ | | | | | | gowin: Add bels for new types of oscillators
| * | gowin: Add bels for new types of oscillatoruis2023-02-062-0/+21
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* | Merge pull request #1087 from yrabbit/gw1nr-9myrtle2023-02-023-46/+65
|\ \ | | | | | | gowin: Add PLL support for the GW1NR-9 chip
| * \ Merge branch 'master' into gw1nr-9YRabbit2023-02-024-24/+52
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* | | Merge pull request #1089 from smunaut/icegatemyrtle2023-02-013-14/+24
|\ \ \ | | | | | | | | ice40: Add support for PLL ICEGATE function
| * | | ice40: Don't assert on unknown extra_config bits if they are 0Sylvain Munaut2023-02-011-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Bits are 0 by default anyway, so if they are unknown (because icestorm is too od) but we want them at 0 ... it's not much of an issue. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * | | ice40: Add support for PLL ICEGATE functionSylvain Munaut2023-02-013-13/+19
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | Technically you can enable it independently on CORE and GLOBAL output, but this is not exposed in the classic primitive, so we do the same as icecube2 and enable/disable it for both output path depending on the argument Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | | Merge pull request #1088 from rowanG077/ecp5-singleton-lpfmyrtle2023-01-311-1/+8
|\ \ \ | |_|/ |/| | ecp5: LOCATE in LPF works on singleton vector
| * | ecp5: LOCATE in LPF works on singleton vectorrowanG0772023-01-311-1/+8
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* | Merge pull request #1086 from smunaut/out_zmyrtle2023-01-301-9/+20
|\ \ | | | | | | ice40: Improve `output` handling vs pull-ups and undriven
| * | ice40: Support for undriven / unconnected output portsSylvain Munaut2023-01-291-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | If a port specified as output (and thus had a $nextpnr_obuf inserted) is undriven (const `z` or const `x`), we make sure to not enable the output driver. Also enable pull-ups if it was requested by the user. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * | ice40: Rework pull-up attribute copy to SB_IO blocksSylvain Munaut2023-01-291-8/+14
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | We try to copy the attribute only when there is a chance for the output driver to not be active. Note that this can _also_ happen when a port is specified as output but has a TBUF, which the previous code wasn't handling. We could copy the attribute "all-the-time" but this would mean if a user specified a `-pullup yes` in the PCF for a permanently driven output pin, we'd be burning power for nothing. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
| * gowin: Add PLL support for the GW1NS-2C chipYRabbit2023-01-312-1/+8
| | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| * gowin: Add PLL support for GW1NR-4 chipsYRabbit2023-01-312-2/+6
| | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| * gowin: Proper use of the C++ mechanismsYRabbit2023-01-302-10/+8
| | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| * gowin: Add PLL support for the GW1NR-9 chipYRabbit2023-01-303-46/+56
|/ | | | | | | | | And also unified the fixing of PLL to bels: the point is that PLL being at a certain location has the possibility to use a direct implicit wire to the clock source, but once we decide to use this direct wire, the PLL can no longer be moved. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Merge pull request #1084 from YosysHQ/gatecat/ecp5-ioff-fixmyrtle2023-01-271-8/+24
|\ | | | | ecp5: Improve IOFF CE handling robustness
| * ecp5: Improve IOFF CE handling robustnessgatecat2023-01-251-8/+24
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #1085 from yrabbit/gw1nr-9c-pllmyrtle2023-01-277-104/+125
|\ \ | | | | | | gowin: Add PLL support for the GW1NR-9C chip
| * | gowin: Add PLL support for the GW1NR-9C chipYRabbit2023-01-267-104/+125
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This chip is used in the Tangnano9k board. * all parameters of the rPLL primitive are supported; * all PLL outputs are treated as clock sources and optimized routing is applied to them; * primitive rPLL on different chips has a completely different structure: for example in GW1N-1 it takes two cells, and in GW1NR-9C as many as four, despite this unification was carried out and different chips are processed by the same functions, but this led to the fact that you can not use the PLL chip GW1N-1 with the old apicula bases - will issue a warning and refuse to encode primitive. In other cases compatibility is supported. * Cosmetic change: the usage report shows the rPLL names without any service bels. * I use ctx->idf() on occasion, it's not a total redesign. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* / clangformatgatecat2023-01-255-68/+47
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #1081 from danc86/eigen-cmake-imported-targetmyrtle2023-01-241-2/+1
|\ | | | | use eigen as an IMPORTED target in CMake
| * use eigen as an IMPORTED target in CMakeDan Callaghan2023-01-241-2/+1
|/ | | | | | | | | | Eigen considers the EIGEN3_INCLUDE_DIRS and EIGEN3_DEFINITIONS variables to be deprecated and they will no longer be exported in the next release after 3.4.0: https://gitlab.com/libeigen/eigen/-/commit/f2984cd0778dd0a1d7e74216d826eaff2bc6bfab Use the IMPORTED target instead, which seems to be the preferred way of consuming third-party CMake libraries.
* Merge pull request #1080 from YosysHQ/gatecat/missing-includesmyrtle2023-01-239-3/+13
|\ | | | | Add missing <set> includes
| * Add missing <set> includesgatecat2023-01-209-3/+13
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #1077 from yrabbit/gw1nsr-4c_0myrtle2023-01-197-38/+209
|\ | | | | gowin: add a PLL primitive for the GW1NS-4 series
| * gowin: improve error messageYRabbit2023-01-191-1/+2
| | | | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| * gowin: to use the FB network detection functionYRabbit2023-01-191-0/+6
| | | | | | | | | | | | | | The chip used in tangnano4k does not have such pins, but we call the function anyway in the expectation of other chips. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| * gowin: add a PLL primitive for the GW1NS-4 seriesYRabbit2023-01-187-38/+202
| | | | | | | | | | | | | | | | | | | | * both instances of the new PLLVR type are supported; * primitive placement is optimized for the use of dedicated PLL clock pins; * all 4 outputs of each primitive can use the clock nets (only 5 lines in total at the same time so far). Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | Merge pull request #1078 from YosysHQ/gatecat/route-delay-quadmyrtle2023-01-183-1/+49
|\ \ | |/ |/| context: Add getNetinfoRouteDelayQuad
| * context: Add getNetinfoRouteDelayQuadgatecat2023-01-183-1/+49
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #1076 from adamgreig/ecp5-dsp-remapmyrtle2023-01-044-1/+281
|\ | | | | ECP5: Add DSP signal remapping
| * Add remapping of DSP clk/ce/rst signals in a block.Adam Greig2023-01-044-0/+280
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Each DSP block contains two slices, and each slice contains multiple MULT18X18D and ALU54B units. Each unit configures each register to use any of CLK0/1/2/3, CE0/1/2/3, and RST0/1/2/3 ports, and the ports are connected per unit (so for example, two MULTs in the same block could connect their CLK0s to different external signals). However, the hardware only has one actual port per block, so it's required that all CLK0 signals within a block are the same. Because the packer is in general allowed to combine two unrelated units into one block, it may end up combining units that use different signals for the same port, which would eventually have caused a router failure. This commit adds validity checks which ensure only unique signals are used per block, and adds remapping so that conflicting signals are automatically reassigned when possible and required.
| * Include ALU54B in cell types with wire location overridesAdam Greig2023-01-041-1/+1
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* clangformatgatecat2023-01-022-4/+8
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #1075 from YosysHQ/gatecat/ecp5-lpf-errorsmyrtle2023-01-021-9/+10
|\ | | | | ecp5: Improve error handling for missing end-"
| * ecp5: Improve error handling for missing end-"gatecat2023-01-021-9/+10
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #1073 from yrabbit/docmyrtle2023-01-011-3/+3
|\ | | | | doc: fix the list format
| * doc: fix the list formatYRabbit2023-01-011-3/+3
|/ | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Merge pull request #1071 from yrabbit/to-floatmyrtle2022-12-305-50/+85
|\ | | | | gowin: bugfix and improved clock router
| * gowin: improve clock wire routingYRabbit2022-12-305-45/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The dedicated router for clock wires now understands not only the IO pins but also the rPLL outputs as clock sources. This simple router sets an optimal route, so it is now the default router. It can be disabled with the --disable-globals command line flag if desired, but this is not recommended due to possible clock skew. Still for GW1N-4C there is no good router for clock wires as there external quartz resonator is connected via PLL. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
| * gowin: correct the delay calculationYRabbit2022-12-291-5/+16
|/ | | | | | | And do a full enumeration when searching for a delay because it is not yet clear whether the orderliness of the vector is guaranteed. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-19 15:24:42 +0000