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* Merge pull request #889 from YosysHQ/gatecat/generic-refactorgatecat2021-12-308-228/+348
|\ | | | | generic: Refactor for faster performance
| * generic: Refactor for faster performancegatecat2021-12-308-228/+348
|/ | | | | | | | This won't affect Python-built arches significantly; but will be useful for the future 'viaduct' functionality where generic routing graphs can be built on the C++ side; too. Signed-off-by: gatecat <gatecat@ds0.me>
* docs: Fix typogatecat2021-12-291-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #877 from pepijndevos/patch-3gatecat2021-12-262-2/+2
|\ | | | | Add support for GW1NS-4 series devices
| * update release that actually includes GW1NS-4 chipdbPepijn de Vos2021-12-261-1/+1
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| * build on release of apycula with gw1ns-4 supportPepijn de Vos2021-12-241-1/+1
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| * Add support for GW1NS-4 series devicesPepijn de Vos2021-12-241-1/+1
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* | Merge pull request #888 from yrabbit/dim-xygatecat2021-12-261-1/+1
|\ \ | | | | | | gowin: Initializing the grid dimensions
| * | gowin: Initializing the grid dimensionsYRabbit2021-12-261-1/+1
|/ / | | | | | | | | | | | | gridDimX and gridDimY are not initialized explicitly, which leads to effects when the design is reloaded, say, from the GUI. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | Merge pull request #884 from yrabbit/simplified-io-prgatecat2021-12-244-4/+77
|\ \ | |/ |/| gowin: Add simplified IO cells processing
| * gowin: Add simplified IO cells processingYRabbit2021-12-204-4/+77
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some models have I/O cells that are IOBUFs, and other types (IBUFs and OBUFs) are obtained by feeding 1 or 0 to the OEN input. This is done with general-purpose routing so it's best to do it here to avoid conflicts. For this purpose, in the new bases, these special cells are of type IOBS (IOB Simplified). The proposed changes are compatible with bases of previous versions of Apycula and do not require changing .CST constraint files. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | Merge pull request #887 from YosysHQ/gatecat/mistral-bit-updategatecat2021-12-222-2/+2
|\ \ | | | | | | mistral: Update to latest enum name
| * | mistral: Update to latest enum namegatecat2021-12-222-2/+2
|/ / | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #885 from antmicro/nexus-slewrategatecat2021-12-213-2/+10
|\ \ | |/ |/| nexus: handle SLEWRATE in pdc
| * nexus: handle SLEWRATE in pdcKarol Gugala2021-12-203-2/+10
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* Merge pull request #883 from YosysHQ/gatecat/new-predictdelaygatecat2021-12-1926-70/+89
|\ | | | | archapi: Use arbitrary rather than actual placement in predictDelay [breaking change]
| * archapi: Use arbitrary rather than actual placement in predictDelaygatecat2021-12-1926-70/+89
|/ | | | | | | | | | | | This makes predictDelay be based on an arbitrary belpin pair rather than a arc of a net based on cell placement. This way 'what-if' decisions can be evaluated without actually changing placement; potentially useful for parallel placement. A new helper predictArcDelay behaves like the old predictDelay to minimise the impact on existing passes; only arches need be updated. Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #882 from YosysHQ/gatecat/router1-tmg-ripupgatecat2021-12-183-6/+103
|\ | | | | router1: Experimental timing-driven ripup support
| * router1: Experimental timing-driven ripup supportgatecat2021-12-183-6/+103
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #881 from uis246/regexgatecat2021-12-181-6/+2
|\ \ | | | | | | Tidy gowin modification regex
| * | Clean gowin modification regexuis2021-12-181-6/+2
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* | | Merge pull request #880 from YosysHQ/gatecat/router1-heuristicgatecat2021-12-181-13/+25
|\ \ \ | |/ / |/| / | |/ router1: Improve timing heuristic
| * router1: Improve timing heuristicgatecat2021-12-181-13/+25
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #879 from YosysHQ/gatecat/nexus-867gatecat2021-12-182-2/+73
|\ | | | | nexus: router1 speedup based on #867
| * nexus: router1 speedup based on #867gatecat2021-12-172-2/+73
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #878 from YosysHQ/gatecat/fix-876gatecat2021-12-171-1/+1
|\ \ | |/ |/| frontend: Consider net aliases when uniquifying name
| * frontend: Consider net aliases when uniquifying namegatecat2021-12-171-1/+1
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #858 from cr1901/machxo2gatecat2021-12-179-18/+83
|\ | | | | MachXO2 Checkpoint 2
| * clangformat.William D. Jones2021-12-162-9/+12
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| * README.md: Add machxo2 arch to list of (experimental) supported devices.William D. Jones2021-12-161-0/+1
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| * machxo2: Remove no-iobs option. It was always enabled and should remain an ↵William D. Jones2021-12-166-8/+5
| | | | | | | | implementation detail.
| * machxo2: Remove -noiopad option when generating miters for post-pnr ↵William D. Jones2021-12-161-1/+2
| | | | | | | | verification.
| * machxo2: Add packing logic to forbid designs lacking FACADE_IO top-level ports.William D. Jones2021-12-161-0/+46
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| * machxo2: Correct which PIO wires get adjusted when writing text bitstream. ↵William D. Jones2021-12-161-9/+26
|/ | | | Add verbose logging for adjustments.
* Merge pull request #874 from yrabbit/modelsgatecat2021-12-151-1/+1
|\ | | | | gowin: Recognize models correctly
| * gowin: Recognize models correctlyYRabbit2021-12-151-1/+1
|/ | | | | | | | | | | For example, clearly distinguish between GW1N-4 GW1NR-4 GW1NS-4 GW1NSR-4 GW1NSR-4 Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Merge pull request #872 from YosysHQ/gatecat/py-loc-apigatecat2021-12-142-1/+8
|\ | | | | python: Bind getBelLocation/getPipLocation
| * python: Bind getBelLocation/getPipLocationgatecat2021-12-142-1/+8
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #870 from YosysHQ/gatecat/ecp5-lutpermgatecat2021-12-148-8/+118
|\ | | | | ecp5: LUT permutation support
| * ecp5: LUT permutation supportgatecat2021-12-138-8/+118
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #871 from yrabbit/englishgatecat2021-12-141-4/+4
|\ \ | |/ |/| gowin: Fix spelling of messages
| * gowin: Fix spelling of messagesYRabbit2021-12-141-4/+4
|/ | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Merge pull request #868 from mkj/mkj/chipdb-16bitgatecat2021-12-132-14/+15
|\ | | | | ecp5: Reduce some chipdb fields from 32 to 16 bit
| * ecp5: Reduce some chipdb fields sizesMatt Johnston2021-12-132-14/+15
|/ | | | This reduces the final binary size by ~7 MB for 85k
* clangformatgatecat2021-12-122-7/+9
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* router2: Improve reservation debug logginggatecat2021-12-121-2/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #867 from mkj/mkj/routerspeed2gatecat2021-12-124-16/+107
|\ | | | | Improvements to ecp5 router speed
| * ecp5: Keep "visited" localMatt Johnston2021-12-121-2/+1
| | | | | | | | Otherwise it keeps growing boundless and slows down small arcs
| * ecp5: Use a vector rather than dictMatt Johnston2021-12-123-14/+106
| | | | | | | | | | This improves router1 performance vs the default dict Using it for wire2net, pip2net, wire_fanout
* | Merge pull request #869 from YosysHQ/gatecat/mistral-route-fixgatecat2021-12-122-3/+3
|\ \ | | | | | | mistral: DATAIN and DATAOUT of GPIO have swapped
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