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* interchange: phys: do not output nets which have no usersAlessandro Comodi2021-07-011-1/+12
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* Merge pull request #741 from acomodi/fix-ded-intercgatecat2021-06-301-8/+14
|\ | | | | interchange: fix dedicated interconnect exploration
| * interchange: fix dedicated interconnect explorationAlessandro Comodi2021-06-301-8/+14
|/ | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* Merge pull request #739 from YosysHQ/gatecat/usp-io-macrogatecat2021-06-305-1/+91
|\ | | | | interchange: Place entire IO macro based on routeability
| * interchange: Fix dedicated interconnect check when site is the samegatecat2021-06-301-1/+4
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * interchange: Place IO macro content based on routinggatecat2021-06-301-0/+79
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * interchange: Track the macros that cells have been expanded fromgatecat2021-06-293-0/+8
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #738 from YosysHQ/json_load_reinitgatecat2021-06-303-11/+11
|\ \ | | | | | | Preserve ArchArgs and reinit Context when applicable in GUI, fixes #737
| * | Preserve ArchArgs and reinit Context when applicable in GUIMiodrag Milanovic2021-06-303-11/+11
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* / loading json should be disabled in this placeMiodrag Milanovic2021-06-301-1/+1
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* Merge pull request #736 from YosysHQ/gatecat/pp-multi-outputgatecat2021-06-281-13/+2
|\ | | | | interchange: Allow site wires driven by more than one bel
| * interchange: Allow site wires driven by more than one belgatecat2021-06-281-13/+2
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #735 from YosysHQ/gatecat/ic-disconn-belpingatecat2021-06-281-1/+1
|\ \ | |/ |/| interchange: Handle disconnected bel pins in dedicated interconnect
| * interchange: Handle disconnected bel pins in dedicated interconnectgatecat2021-06-281-1/+1
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #734 from acomodi/remove-rw-patchgatecat2021-06-241-3/+0
|\ | | | | ci: remove RapidWright patching
| * ci: remove RapidWright patchingAlessandro Comodi2021-06-241-3/+0
|/ | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* Merge pull request #733 from acomodi/interchange-move-macro-before-iogatecat2021-06-181-1/+1
|\ | | | | interchange: arch: move macro expansion step before ios packing
| * interchange: arch: move macro expansion step before ios packingAlessandro Comodi2021-06-181-1/+1
|/ | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* Merge pull request #731 from YosysHQ/gatecat/timing-mem-errorgatecat2021-06-171-4/+11
|\ | | | | sta: Fix a memory error introduced by using dict instead of unordered_map
| * sta: Fix a memory error introduced by the dict movegatecat2021-06-171-4/+11
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #730 from YosysHQ/gatecat/dcc-routehtrugatecat2021-06-173-3/+62
|\ | | | | nexus: Fix some 17k reliability issues
| * nexus: Disable center DCC-thrus on 17k devicegatecat2021-06-163-1/+29
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * nexus: Fix FASM gen for DCC-thrugatecat2021-06-161-3/+34
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #728 from YosysHQ/gatecat/nexus-ramgatecat2021-06-157-2/+384
|\ | | | | interchange/nexus: Add RAM techmap rule and a RAM test
| * interchange: Bump versionsgatecat2021-06-151-2/+2
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * nexus: Add modified version of RAM testgatecat2021-06-155-0/+206
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * nexus: Add PDPSC16K->PDPSC16K_MODE to remap rulesgatecat2021-06-151-0/+176
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #729 from acomodi/interchange-fix-phys-net-writergatecat2021-06-151-5/+2
|\ \ | | | | | | interchange: fix phys net writer
| * | interchange: fix phys net writerAlessandro Comodi2021-06-151-5/+2
|/ / | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* | Merge pull request #727 from YosysHQ/gatecat/ic-undrivengatecat2021-06-143-5/+9
|\| | | | | interchange: Cope with undriven nets in more places
| * interchange: Cope with undriven nets in more placesgatecat2021-06-143-5/+9
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #724 from YosysHQ/gatecat/update-namesgatecat2021-06-12204-282/+282
|\ | | | | Update deadnames and emails
| * Bump tests submodulegatecat2021-06-121-0/+0
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * Update URLsgatecat2021-06-123-9/+9
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * Fixing old emails and names in copyrightsgatecat2021-06-12201-273/+273
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #726 from YosysHQ/gatecat/mem-errorsgatecat2021-06-121-1/+1
|\ \ | |/ |/| HeAP: Fix memory error introduced by switch to dict
| * HeAP: Fix memory error introduced by switch to dictgatecat2021-06-121-1/+1
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #720 from acomodi/interchange-clustersgatecat2021-06-1113-30/+715
|\ | | | | interchange: enable clusters support
| * interchange: ci: add RW patch for missing cell bel mapsAlessandro Comodi2021-06-111-0/+3
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| * interchange: clusters: always get cell bel map and add assertsAlessandro Comodi2021-06-111-23/+13
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| * interchange: ci: update python-interchange tagAlessandro Comodi2021-06-111-1/+1
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| * interchange: run clang formatterAlessandro Comodi2021-06-112-22/+18
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| * interchange: clusters: adjust commentsAlessandro Comodi2021-06-112-11/+16
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| * interchange: increase chipinfo versionAlessandro Comodi2021-06-111-1/+1
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| * interchange: tests: counter: emit carries for xc7Alessandro Comodi2021-06-112-4/+6
| | | | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
| * interchange: add support for generating BEL clustersAlessandro Comodi2021-06-119-24/+713
|/ | | | | | | | Clustering greatly helps the placer to identify and pack together specific cells at the same site (e.g. LUT+FF), or cells that are chained through dedicated interconnections (e.g. CARRY CHAINS) Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* Merge branch 'test_framework'gatecat2021-06-112-0/+3
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| * fpga_interchange: Add site router testsTomasz Michalak2021-06-111-0/+3
| | | | | | | | Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
| * tests: fpga_interchange: Update module to use site router test frameworkTomasz Michalak2021-06-111-0/+0
|/ | | | Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
* ecp5: Add missing clock edge assignmentsgatecat2021-06-101-0/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
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