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* Bump tests submodule.Keith Rothman2021-02-241-0/+0
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Fix some bugs found in review.Keith Rothman2021-02-241-5/+2
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add dynamic bitarray to common library.Keith Rothman2021-02-231-0/+82
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Merge pull request #594 from YosysHQ/gatecat/heap-tidyinggatecat2021-02-236-41/+88
|\ | | | | Tidying up HeAP
| * Refactor some common code to CellInfo methodsgatecat2021-02-236-38/+43
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * HeAP: Document legalise_placement_strict bettergatecat2021-02-231-3/+45
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* nexus: Fix getPipDelay returning negative after refactorgatecat2021-02-231-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* pyconsole: Avoid lockup when reading from stdingatecat2021-02-221-0/+2
| | | | | | | | Create an empty temporary file for stdin; so reads fail rather than locking up (otherwise doing help() would be enough to completely lock up the GUI). Signed-off-by: gatecat <gatecat@ds0.me>
* Demote the 'no clocks' warning to info and make clearergatecat2021-02-201-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #592 from YosysHQ/gatecat/rework-delaygatecat2021-02-2035-502/+307
|\ | | | | Replace DelayInfo with DelayPair and DelayQuad
| * Update generic.mdgatecat2021-02-201-4/+4
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * python: Bindings for DelayPair and DelayQuadgatecat2021-02-191-0/+25
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-1933-498/+243
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This replaces the arch-specific DelayInfo structure with new DelayPair (min/max only) and DelayQuad (min/max for both rise and fall) structures that form part of common code. This further reduces the amount of arch-specific code; and also provides useful data structures for timing analysis which will need to delay with pairs/quads of delays as it is improved. While there may be a small performance cost to arches that didn't separate the rise/fall cases (arches that aren't currently separating the min/max cases just need to be fixed...) in DelayInfo, my expectation is that inlining will mean this doesn't make much difference. Signed-off-by: gatecat <gatecat@ds0.me>
| * Add DelayPair and DelayQuad structuresgatecat2021-02-191-0/+35
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | clangformatgatecat2021-02-191-1/+2
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #576 from litghost/add_cell_bel_pin_mappinggatecat2021-02-1928-86/+2251
|\ | | | | Complete FPGA interchange Arch to the point where it can route a wire
| * Fix sign mismatch.Keith Rothman2021-02-182-2/+2
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Do some spell checking on site_router.ccKeith Rothman2021-02-181-18/+18
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Add some utility methods for site instance access.Keith Rothman2021-02-183-13/+42
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Update README's with latest instructions and features.Keith Rothman2021-02-183-20/+94
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Update tests library to include Bits unit test.Keith Rothman2021-02-171-0/+0
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Add utility targets for getting plain text outputs.Keith Rothman2021-02-171-1/+5
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Add IOSTANDARD to ports.Keith Rothman2021-02-171-1/+3
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Emit fixed attributes to output physical netlist.Keith Rothman2021-02-171-8/+19
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Use Bits library for bit instrisics.Keith Rothman2021-02-171-2/+4
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Refactor "get only from iterator" to a utility.Keith Rothman2021-02-174-12/+32
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Keep all build artifacts under create_bba/build.Keith Rothman2021-02-172-4/+5
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Change how package pin IO sites are selected.Keith Rothman2021-02-173-16/+52
| | | | | | | | | | | | | | The first site type that matches is now selected, under the premise that the early site types are more general. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Change makefiles to build a FPGA interchange BBA.Keith Rothman2021-02-174-16/+106
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Add examples invoking FPGA interchange nextpnr.Keith Rothman2021-02-1711-0/+152
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Continue fixes.Keith Rothman2021-02-176-23/+97
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Disable traversal limit when reading logical netlist.Keith Rothman2021-02-171-1/+3
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Add initial site router.Keith Rothman2021-02-174-6/+813
| | | | | | | | | | | | | | | | This site router likely cannot handle the full problem space. It may need to be replaced with a more generalize approach as testing continues. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Working on standing up initial constraints system.Keith Rothman2021-02-178-25/+886
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #588 from YosysHQ/gatecat/gowin-fixesgatecat2021-02-183-14/+21
|\ \ | | | | | | Gowin regression fixes
| * | gowin: Fix archcheck errors and add to CIgatecat2021-02-172-1/+12
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * | gowin: Use base bel bucket/cell type methodsgatecat2021-02-171-5/+1
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
| * | gowin: Fix IdStrings being overwritten by wireToGlobalgatecat2021-02-171-8/+8
| | | | | | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | | Merge pull request #590 from cbalint13/mastergatecat2021-02-182-4/+32
|\ \ \ | | | | | | | | Expose ice40 arch placer-heap internal parameters.
| * | | Expose ice40 arch placer-heap internal parameters.Balint Cristian2021-02-182-4/+32
|/ / /
* | / Bump tests submodule to include bits testsgatecat2021-02-171-0/+0
| |/ |/| | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #589 from litghost/add_bits_librarygatecat2021-02-172-0/+124
|\ \ | |/ |/| Add a Bits utility library.
| * Add a Bits utility library.Keith Rothman2021-02-172-0/+124
|/ | | | | | | This library captures use of __builtin_popcount and __builtin_ctz on GCC/clang and hopefully handles the MSVC case. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Update docs/archapi.mdgatecat2021-02-171-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #587 from YosysHQ/gatecat/generic-vccgatecat2021-02-172-5/+7
|\ | | | | generic: Don't generate Vcc if not needed
| * generic: Don't generate Vcc if not neededgatecat2021-02-172-5/+7
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | clangformatgatecat2021-02-171-3/+4
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #586 from litghost/add_cell_bel_mapping_onlygatecat2021-02-172-13/+274
|\ | | | | Add Cell -> BEL Pin maps to FPGA interchange arch.
| * Require `--package` when arch BBA contains multiple packages.Keith Rothman2021-02-161-3/+11
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * [FPGA Interchange] Add Cell -> BEL Pin maps.Keith Rothman2021-02-162-13/+266
| | | | | | | | | | | | | | This also expands the FPGA interchange Arch BBA to include placement constraints, but doesn't implement them yet. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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