aboutsummaryrefslogtreecommitdiffstats
Commit message (Expand)AuthorAgeFilesLines
...
* | Merge pull request #56 from YosysHQ/q3k/issue-55Serge Bazanski2018-08-192-12/+28
|\ \
| * | ice40: make PLL packing more robustSergiusz Bazanski2018-08-192-12/+28
* | | fix zoom on elements, fixes #61Miodrag Milanovic2018-08-191-1/+1
* | | Merge pull request #60 from YosysHQ/ice40uiClifford Wolf2018-08-193-14/+95
|\ \ \
| * | | Add more missing iCE40 gfx (LP/HX is complete now)Clifford Wolf2018-08-193-4/+47
| * | | Add iCE40 gfx for carry chain pips and LUT cascade pipsClifford Wolf2018-08-191-5/+43
| * | | Fix iCE40 pip gfx for pips on the top edge of a switchboxClifford Wolf2018-08-191-5/+5
* | | | ecp5: clangformatDavid Shah2018-08-191-27/+19
* | | | Merge pull request #59 from daveshah1/ecp5_timingDavid Shah2018-08-193-16/+178
|\ \ \ \ | |/ / / |/| | |
| * | | ecp5: Fix delay heuristicDavid Shah2018-08-191-2/+2
| * | | ecp5: Add cell delaysDavid Shah2018-08-191-11/+131
| * | | ecp5: Add crude approximation of Pip delaysDavid Shah2018-08-192-3/+45
* | | | Merge pull request #58 from YosysHQ/ice40uiClifford Wolf2018-08-195-10/+162
|\ \ \ \ | |/ / / |/| | |
| * | | Add iCE40 gfx for IO span-4 cornersClifford Wolf2018-08-193-3/+36
| * | | Add iCE40 gfx for span-4 wires between IO tilesClifford Wolf2018-08-195-7/+126
| |/ /
* | | Merge pull request #54 from daveshah1/ecp5_speedupDavid Shah2018-08-195-29/+63
|\ \ \ | |/ / |/| |
| * | ecp5: Flatten bel_to_cell for performanceDavid Shah2018-08-182-23/+21
| * | ecp5: Speed up Bel availability/binding checksDavid Shah2018-08-181-5/+11
| * | ecp5: Speedup placement using ArchCellInfoDavid Shah2018-08-184-12/+42
* | | Merge pull request #47 from YosysHQ/settings_propagateClifford Wolf2018-08-1817-41/+130
|\ \ \
| * | | Use emplace result for get,set of settingsMiodrag Milanovic2018-08-121-8/+8
| * | | Read settings and check validityMiodrag Milanovic2018-08-112-6/+28
| * | | Save settings and give nicer names to someMiodrag Milanovic2018-08-106-7/+15
| * | | Use settings for placer1 and router1Miodrag Milanovic2018-08-0911-34/+93
* | | | Merge pull request #53 from YosysHQ/archattrClifford Wolf2018-08-1813-26/+644
|\ \ \ \
| * | | | Add iCE40 gfx for wires connecting fabric tiles and IO tilesClifford Wolf2018-08-184-2/+261
| * | | | Improve iCE40 gfx for IO tiles and RAM tilesClifford Wolf2018-08-185-23/+243
| * | | | Add ice40 wire attributes (grid position, segment list)Clifford Wolf2018-08-183-18/+45
| * | | | Add arch attributes display to GUIClifford Wolf2018-08-181-0/+15
| * | | | Add stringf() helper functionClifford Wolf2018-08-182-0/+15
| * | | | Merge branch 'master' of github.com:YosysHQ/nextpnr into archattrClifford Wolf2018-08-184-7/+23
| |\ \ \ \ | | | |/ / | | |/| |
| * | | | Add Arch attrs APIClifford Wolf2018-08-145-0/+82
* | | | | Merge pull request #51 from YosysHQ/json-updateClifford Wolf2018-08-181-9/+23
|\ \ \ \ \ | |_|/ / / |/| | | |
| * | | | JSON-PARSER: Fixed bug in properly reading neg #sZipCPU2018-08-151-2/+2
| | |_|/ | |/| |
| * | | Fixed JSON parser: negative values and line numbersZipCPU2018-08-141-9/+23
| |/ /
* | | ecp5: Speedup router with slightly better estimatesDavid Shah2018-08-181-2/+2
* | | do not break if there are no nets loaded from sym sectionMiodrag Milanovic2018-08-181-4/+6
* | | Added ability for static buildsMiodrag Milanovic2018-08-162-1/+15
|/ /
* | Merge pull request #48 from YosysHQ/placer_speedupEddie Hung2018-08-114-32/+66
|\ \ | |/ |/|
| * Merge remote-tracking branch 'origin/master' into placer_speedupEddie Hung2018-08-1012-36/+116
| |\ | |/ |/|
* | Fix compile warningMiodrag Milanovic2018-08-091-0/+2
* | Expose log_always that will be displayed disregarding quite flagMiodrag Milanovic2018-08-092-12/+10
* | Added quiet mode for loggingMiodrag Milanovic2018-08-093-15/+28
* | Fix MSVC compileMiodrag Milanovic2018-08-091-0/+1
* | Merge pull request #42 from YosysHQ/floorplanDavid Shah2018-08-098-20/+86
|\ \
| * | ecp5: Implement getPipLocation and related APIDavid Shah2018-08-091-1/+11
| * | Add pip locationsClifford Wolf2018-08-097-19/+61
| * | Add Region structClifford Wolf2018-08-091-0/+14
| | * Rework Arch::logicCellsCompatible() to take pointer + size, allowing use of s...Eddie Hung2018-08-103-17/+18
| | * std::vector::resize() not reserve()Eddie Hung2018-08-091-1/+1