| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | common: disable parallel refinement only without threads. | Catherine | 2023-02-23 | 1 | -1/+1 |
| | | | | | Previously it was always disabled on WebAssembly builds. | ||||
| * | common: update deprecated use of `boost::filesystem::basename`. | Catherine | 2023-02-23 | 1 | -2/+2 |
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| * | common: add missing includes for libc++. | Catherine | 2023-02-23 | 2 | -0/+3 |
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| * | Include <cstdint> in common/kernel/hashlib.h | Thomas W Rodgers | 2023-02-18 | 1 | -0/+1 |
| | | | | | | | | The definitions for uint32_t, uint64_t report as undefined when compiling under GCC13. They were previously found by transitive includes, but this is not guaranteed to work, and GCC13 forced the issue. | ||||
| * | common: Print out generated seed value | rowanG077 | 2023-02-16 | 1 | -1/+3 |
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| * | common: Implement Werror flag | rowanG077 | 2023-02-13 | 3 | -9/+29 |
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| * | clangformat | gatecat | 2023-01-25 | 1 | -1/+4 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Add missing <set> includes | gatecat | 2023-01-20 | 1 | -0/+2 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | context: Add getNetinfoRouteDelayQuad | gatecat | 2023-01-18 | 3 | -1/+49 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | clangformat | gatecat | 2023-01-02 | 1 | -2/+3 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Remove deprecated functions | Miodrag Milanovic | 2022-12-22 | 3 | -26/+4 |
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| * | Set divisor instead of absolute value | Arjen Roodselaar | 2022-12-20 | 1 | -1/+1 |
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| * | Allow setting cell placement timeout | Arjen Roodselaar | 2022-12-20 | 1 | -3/+5 |
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| * | Add --no-placer-timeout flag to override timeout during refinement | Arjen Roodselaar | 2022-12-19 | 1 | -0/+4 |
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| * | api: add explain_invalid option to isBelLocationValid | gatecat | 2022-12-07 | 3 | -4/+4 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | refactor: ArcBounds -> BoundingBox | gatecat | 2022-12-07 | 3 | -8/+8 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | api: Make NetInfo* of checkPipAvailForNet const | gatecat | 2022-12-02 | 2 | -2/+2 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Fix "implicit copy constructor for 'Property' is deprecated" | gatecat | 2022-11-10 | 1 | -0/+1 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | run clangformat | gatecat | 2022-10-17 | 1 | -6/+10 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Modify code to meet the code style preferences | airskywater | 2022-09-24 | 1 | -4/+4 |
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| * | Add more sanity check for pointers | airskywater | 2022-09-24 | 1 | -0/+1 |
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| * | fix runtime segmentation fault | airskywater | 2022-09-24 | 1 | -0/+5 |
| | | | | disable null pointer dereference! | ||||
| * | Added the --ignore-rel-clk option to control timing checks for cross-domain ↵ | Maciej Kurc | 2022-09-20 | 3 | -115/+108 |
| | | | | | | | paths, formatted code Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| * | Code cleanup | Maciej Kurc | 2022-08-31 | 1 | -64/+35 |
| | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| * | Added timing check for cross-domain paths for related clocks | Maciej Kurc | 2022-08-31 | 1 | -4/+104 |
| | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| * | Augmented TimingAnalyser class with detection of clock to clock relations | Maciej Kurc | 2022-08-30 | 2 | -7/+225 |
| | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| * | add missing overrides | Miodrag Milanovic | 2022-08-22 | 1 | -3/+3 |
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| * | pybindings: Mark CellInfo::bel as readonly | gatecat | 2022-08-18 | 1 | -2/+1 |
| | | | | | | | | | bel bindings should be updated with bindBel/unbindBel during placement, or setting the BEL attribute for constraints before placement. Fixes #522 Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | refactor: id(stringf(...)) to new idf(...) helper | gatecat | 2022-08-10 | 3 | -4/+18 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | netlist: Add PseudoCell API | gatecat | 2022-07-08 | 7 | -28/+127 |
| | | | | | | | | | | | | | | | | When implementing concepts such as partition pins or deliberately split nets, there's a need for something that looks like a cell (starts/ends routing with pins on nets, has timing data) but isn't mapped to a fixed bel in the architecture, but instead can have pin mappings defined at runtime. The PseudoCell allows this by providing an alternate, virtual-function based API for such cells. When a cell has `pseudo_cell` used, instead of calling functions such as getBelPinWire, getBelLocation or getCellDelay in the Arch API; such data is provided by the cell itself, fully flexible at runtime regardless of arch, via methods on the PseudoCell implementation. | ||||
| * | generic: Use arch_pybindings_shared | gatecat | 2022-07-04 | 1 | -0/+6 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Don't assert on mixed domain paths in report | gatecat | 2022-05-22 | 1 | -5/+0 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | common: Correct a minor typo in the message | YRabbit | 2022-05-10 | 1 | -1/+1 |
| | | | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou> | ||||
| * | Split up common into kernel,place,route | gatecat | 2022-04-08 | 59 | -0/+12002 |
| Signed-off-by: gatecat <gatecat@ds0.me> | |||||
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index : iCE40/nextpnr | |
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