| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | router1: Add error when dest port has no wire | gatecat | 2023-03-06 | 1 | -0/+4 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Add missing <set> includes | gatecat | 2023-01-20 | 1 | -0/+1 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | refactor: ArcBounds -> BoundingBox | gatecat | 2022-12-07 | 1 | -15/+15 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | router2: Reserve source wire, too | gatecat | 2022-09-20 | 1 | -0/+7 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Fix parameter order | Miodrag Milanovic | 2022-08-22 | 1 | -2/+1 |
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| * | netlist: Add PseudoCell API | gatecat | 2022-07-08 | 1 | -2/+2 |
| | | | | | | | | | | | | | | | | When implementing concepts such as partition pins or deliberately split nets, there's a need for something that looks like a cell (starts/ends routing with pins on nets, has timing data) but isn't mapped to a fixed bel in the architecture, but instead can have pin mappings defined at runtime. The PseudoCell allows this by providing an alternate, virtual-function based API for such cells. When a cell has `pseudo_cell` used, instead of calling functions such as getBelPinWire, getBelLocation or getCellDelay in the Arch API; such data is provided by the cell itself, fully flexible at runtime regardless of arch, via methods on the PseudoCell implementation. | ||||
| * | Split up common into kernel,place,route | gatecat | 2022-04-08 | 4 | -0/+2785 |
| Signed-off-by: gatecat <gatecat@ds0.me> | |||||
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index : iCE40/nextpnr | |
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