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* router2: Add heatmap by routing resource typegatecat2021-05-203-3/+49
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Run clangformatgatecat2021-05-161-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Tidying upgatecat2021-05-152-2/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* router2: Hacky workaround for slow Cyclone V convergencegatecat2021-05-151-3/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* router2: Reduce verbosity when debugginggatecat2021-05-151-0/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* mistral: Add stub pack/place/route functionsgatecat2021-05-151-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* archcheck: Use old connectivity check for CycloneVgatecat2021-05-151-1/+29
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* cyclonev: Add names and archcheck fixesgatecat2021-05-152-0/+22
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* router2: Add some boundness statisticsgatecat2021-05-121-0/+33
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* router2: Fix a typogatecat2021-05-111-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* command: Allow debug output for just placer or routergatecat2021-05-111-0/+11
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* router2: Reserve wires in more complex casesgatecat2021-05-061-13/+39
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* router2: Dynamicly expand bounding box based on congestiongatecat2021-05-061-10/+22
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add stub cluster API impl for remaining archesgatecat2021-05-061-0/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* base_arch: Fix typo in getClusterPlacementgatecat2021-05-061-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Update placers to use new cluster APIsgatecat2021-05-069-344/+149
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add default base implementation of cluster APIgatecat2021-05-063-5/+97
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add BaseClusterInfo for base implementationgatecat2021-05-061-0/+44
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* arch_api: Outline of new cluster APIgatecat2021-05-062-9/+9
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Update bits.hDavid Corrigan2021-04-301-2/+2
| | | Fixed the variable name for windows MSVC builds.
* interchange: Implement getWireTypegatecat2021-04-301-0/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #681 from YosysHQ/gatecat/more-pybindingsgatecat2021-04-151-0/+3
|\ | | | | Add Python bindings for placement tests
| * Add Python bindings for placement testsgatecat2021-04-151-0/+3
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Fix utilisation report when bel buckets are usedgatecat2021-04-151-2/+2
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Hash table refactoringgatecat2021-04-142-50/+28
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* timing: Fix domain init when loops are presentgatecat2021-04-132-58/+73
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #674 from adamgreig/heap-spreader-fixgatecat2021-04-121-0/+4
|\ | | | | HeAP: Skip high-strength cells in both cell loops
| * HeAP: Skip high-strength cells in both cell loops.Adam Greig2021-04-121-0/+4
| | | | | | | | | | | | Previously only the first loop skipped cells with high belStrength, but they can't be processed by the second loop either, so skip them there too.
* | fast_bels: Don't return pointer that might become invalidgatecat2021-04-121-14/+18
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Fix bug in router2 where router may give up too early.Keith Rothman2021-04-061-1/+13
| | | | | | | | | | Was introduced in #612. The logic before was intended to prevent the router from terminating early when not using a bounding box, but the fix in #612 simply removed that, meaning that the router might terminate early incorrectly. The solution here is to only use the toexplore hysteric once a solution is found. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* interchange: Fix illegal placementsgatecat2021-03-301-1/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add initial handling of local site inverters and constant signals.Keith Rothman2021-03-251-2/+3
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Use new parameter definition data in FPGA interchange processing.Keith Rothman2021-03-232-1/+130
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Merge pull request #634 from litghost/add_get_bel_pin_typegatecat2021-03-221-0/+2
|\ | | | | Add getBelPinType to Python interface.
| * Add getBelPinType to Python interface.Keith Rothman2021-03-221-0/+2
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Add "checkPipAvailForNet" to Arch API.Keith Rothman2021-03-223-13/+13
|/ | | | | | | | This is important for distiguishing valid pseudo pips in the FPGA interchange arch. This also avoids a double or triple lookup of pip->net map. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Refactor header structures in FPGA interchange Arch.Keith Rothman2021-03-191-0/+3
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Run "make clangformat". to fix up master.Keith Rothman2021-03-184-4/+3
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Moving hash map/set type selection to header.Keith Rothman2021-03-172-8/+52
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add missing includes to fix WASI build.whitequark2021-03-162-0/+5
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* Use NEXTPNR_NAMESPACE macro's now that headers are seperated.Keith Rothman2021-03-159-23/+29
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Merge pull request #621 from litghost/fix_header_nightmaregatecat2021-03-1530-2395/+3104
|\ | | | | Split nextpnr.h to allow for linear inclusion.
| * Split nextpnr.h to allow for linear inclusion.Keith Rothman2021-03-1530-2395/+3104
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "nextpnr.h" is no longer the god header. Important improvements: - Functions in log.h can be used without including BaseCtx/Arch/Context. This means that log_X functions can be called without included "nextpnr.h" - NPNR_ASSERT can be used without including "nextpnr.h" by including "nextpnr_assertions.h". This allows NPNR_ASSERT to be used safely in any header file. - Types defined in "archdefs.h" are now available without including BaseCtx/Arch/Context. This means that utility classes that will be used inside of BaseCtx/Arch/Context can be defined safely in a self-contained header. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | opt-timing: Skip undriven netsgatecat2021-03-151-0/+2
|/ | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add support for partially routed nets from the placer in router2.Keith Rothman2021-03-122-28/+54
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add diagnostic prints to debug lookahead performance.Keith Rothman2021-03-101-13/+41
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Only depend on Abseil in threaded builds.whitequark2021-03-101-0/+6
| | | | | | Abseil has a hard dependency on threads (not just in the build system but in many places in the base libraries), so there is no way to use it on WASI at the moment.
* Merge pull request #607 from litghost/add_absl_flat_hash_mapgatecat2021-03-091-1/+2
|\ | | | | Add absl::flat_hash_map.
| * Add absl::flat_hash_map.Keith Rothman2021-03-011-1/+2
| | | | | | | | | | | | | | This lowers the CPU cost of using the flat wire map in router2, and should use less memory as well. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #609 from YosysHQ/gatecat/sta-v2gatecat2021-03-098-242/+937
|\ \ | | | | | | Use new timing engine for criticality
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