aboutsummaryrefslogtreecommitdiffstats
path: root/dummy
Commit message (Expand)AuthorAgeFilesLines
* Major performance improvement to placement validity checkDavid Shah2018-06-192-9/+20
* Refactor Arch/Context design hierarchyClifford Wolf2018-06-192-6/+13
* Getting rid of users of old IdString APIClifford Wolf2018-06-181-6/+6
* Getting rid of users of old IdString APIClifford Wolf2018-06-182-1/+4
* Towards IdString as per-context facilityClifford Wolf2018-06-181-1/+1
* Rename chip.h to arch.hClifford Wolf2018-06-182-1/+1
* Updates from clangformatClifford Wolf2018-06-181-8/+2
* Rename Design to Context, derive from Arch instead of instantiatingClifford Wolf2018-06-183-6/+6
* Rename Chip to Arch and ChipArgs to ArchArgsClifford Wolf2018-06-184-47/+45
* Improving code style and fixing dummyDavid Shah2018-06-182-0/+8
* Some refactoring of Chip API (prep for chipdb refactoring)Clifford Wolf2018-06-162-8/+10
* Refactor position/delay estimation APIClifford Wolf2018-06-142-37/+7
* Update chip Graphics APIClifford Wolf2018-06-132-5/+11
* Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnrClifford Wolf2018-06-131-1/+1
|\
| * reveresed logic for enabling main file, and made tests link arch filesMiodrag Milanovic2018-06-121-1/+1
* | Redesign PosInfo APIClifford Wolf2018-06-132-3/+46
|/
* Add fast IdString <-> PortPin conversionClifford Wolf2018-06-121-0/+3
* Fix NEXTPNR_NAMESPACEClifford Wolf2018-06-122-0/+8
* Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnrClifford Wolf2018-06-122-0/+57
|\
| * Implement the placement validity checkerDavid Shah2018-06-122-0/+57
* | Add nextpnr namespaceClifford Wolf2018-06-124-0/+14
|/
* Add "nextpnr.h"Clifford Wolf2018-06-114-8/+7
* Remove pool, dict, vector namespace aliasesClifford Wolf2018-06-112-42/+51
* Add conflicting=false argument to bind gettersClifford Wolf2018-06-112-6/+7
* Draw fpga modelMiodrag Milanovic2018-06-101-0/+24
* Pass design to gui, display chip nameMiodrag Milanovic2018-06-103-1/+6
* Add dummy implementations of dummy Chip APIClifford Wolf2018-06-092-1/+94
* Add very basic routerClifford Wolf2018-06-091-8/+19
* python: Fixing builds as importable moduleDavid Shah2018-06-081-0/+4
* Reformat remaining filesDavid Shah2018-06-081-4/+1
* Fix placer build for dummy archClifford Wolf2018-06-071-0/+11
* Reformat Python bindings and ice40 mainDavid Shah2018-06-072-7/+5
* clang-format for design and chip codebaseClifford Wolf2018-06-072-50/+48
* Fix clang-format include order issuesClifford Wolf2018-06-071-0/+2
* Add ice40 geometry informationClifford Wolf2018-06-061-1/+1
* Update and simplify dummy archClifford Wolf2018-06-064-154/+38
* Initial GUI workMiodrag Milanovic2018-06-051-2/+8
* Replace GuiLine with GraphicElementClifford Wolf2018-06-041-9/+4
* Python bindings working on both architecturesDavid Shah2018-06-021-8/+2
* Simple Python test workingDavid Shah2018-06-021-0/+20
* Add architecture specific Python defsDavid Shah2018-06-021-0/+14
* Add a CMake based build systemDavid Shah2018-06-021-0/+0
* Add DelayInfo structClifford Wolf2018-05-291-1/+9
* Progress in chip.h APIClifford Wolf2018-05-261-4/+13
* Add MakefileClifford Wolf2018-05-263-2/+40
* Directory structureClifford Wolf2018-05-263-0/+218
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-03 00:09:06 +0000