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* ecp5: MULT18X18D timing fixesDavid Shah2020-05-011-10/+26
| | | | Signed-off-by: David Shah <dave@ds0.me>
* No cell delay for clocked MULT18X18DRoss Schlaikjer2020-04-301-0/+2
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* Issue warning for mixed-mode inputsRoss Schlaikjer2020-04-291-24/+11
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* Handle register timing caseRoss Schlaikjer2020-04-291-6/+58
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* Use registered port class on mult18x18Ross Schlaikjer2020-04-291-3/+5
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* Alter MULT18X18D timing db based on register configRoss Schlaikjer2020-04-281-1/+1
| | | | | | | | | | | | | | | If the REG_INPUTA_CLK and REG_INPUTB_CLK values are set, then we should use the faster setup/hold timings for the 18x8 multiplier. Similarly, check the value of REG_OUTPUT_CLK for whether or not to use faster timings for the output. This is based on how I currently understand the registers to work - if anyone knows the actual rules for when each timing applies please do chime in to correct this implementation if necessary. Along the same lines, this PR does not address the case when the pipeline registers are enabled, since it is not clear to me how exactly that affects the timing.
* Merge pull request #423 from rschlaikjer/rschlaikjer-regmode-timing-databaseDavid Shah2020-04-071-4/+2
|\ | | | | Add support for REGMODE to DP16KD
| * Actually just move all the logic to ArchInfoRoss Schlaikjer2020-04-071-15/+2
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| * Extract regmode configuration to ArchInfoRoss Schlaikjer2020-04-071-8/+4
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| * Change timing database lookup based on REGMODE valueRoss Schlaikjer2020-04-071-4/+19
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* | ecp5: Proper support for '12k' deviceDavid Shah2020-03-131-2/+7
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* router2: Improve flow and log outputDavid Shah2020-02-031-1/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Allow selection of router algorithmDavid Shah2020-02-031-2/+16
| | | | Signed-off-by: David Shah <dave@ds0.me>
* router2: Make magic numbers configurableDavid Shah2020-02-031-1/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Improve bounding box accuracyDavid Shah2020-02-031-4/+19
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: router2 main renameDavid Shah2020-02-031-1/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Router2 test integrationDavid Shah2020-02-031-1/+38
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge remote-tracking branch 'origin/master' into mmicko/ecp5_guiMiodrag Milanovic2019-12-281-1/+11
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| * ecp5: Add an error for out-of-sync constids and bbaDavid Shah2019-10-261-0/+3
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * ecp5: Fix routing to shared DSP control inputsDavid Shah2019-10-251-1/+8
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | move bel creation to gfx.ccMiodrag Milanovic2019-12-151-122/+2
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* | fix formatingMiodrag Milanovic2019-12-141-2/+1
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* | more new wires addedMiodrag Milanovic2019-12-141-1/+10
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* | ebr, mult and alu nice displayMiodrag Milanovic2019-12-141-1/+1
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* | clangformat runMiodrag Milanovic2019-12-081-27/+30
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* | display IOs properlyMiodrag Milanovic2019-12-071-21/+5
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* | More bels show properlyMiodrag Milanovic2019-12-071-43/+82
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* | add dcca bels and dummy parts for other belsMiodrag Milanovic2019-12-071-9/+54
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* | more pips, and valid mappingMiodrag Milanovic2019-11-101-4/+4
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* | Draw some pips, fixed H6 and V6Miodrag Milanovic2019-11-091-1/+22
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* | Show V02/V06/H02/H06Miodrag Milanovic2019-10-251-1/+1
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* | Split graphics calls for wires into gfx.ccMiodrag Milanovic2019-10-201-268/+3
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* | muxes only together with slicesMiodrag Milanovic2019-10-201-9/+7
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* | Remove not used lineMiodrag Milanovic2019-10-201-2/+0
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* | Simplify layout of elementsMiodrag Milanovic2019-10-201-170/+114
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* | fix slice wireMiodrag Milanovic2019-10-201-20/+20
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* | bound signalsMiodrag Milanovic2019-10-201-0/+65
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* | more wires between switchboxesMiodrag Milanovic2019-10-201-1/+37
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* | Add more types of wiresMiodrag Milanovic2019-10-201-176/+191
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* | finixed slice wiresMiodrag Milanovic2019-10-201-0/+27
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* | wd wiresMiodrag Milanovic2019-10-201-1/+21
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* | Fix look of some wiresMiodrag Milanovic2019-10-201-6/+9
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* | Add output wiresMiodrag Milanovic2019-10-201-0/+35
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* | fix mux displayMiodrag Milanovic2019-10-201-2/+2
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* | set wire active flagMiodrag Milanovic2019-10-201-1/+1
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* | clk and lsr muxesMiodrag Milanovic2019-10-201-1/+62
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* | draw rest of slice wires and more from switchboxMiodrag Milanovic2019-10-201-3/+52
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* | OptimizeMiodrag Milanovic2019-10-201-12/+4
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* | Add other side of slice wiresMiodrag Milanovic2019-10-201-9/+24
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* | Display rest of slice input wiresMiodrag Milanovic2019-10-201-2/+8
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