Commit message (Collapse) | Author | Age | Files | Lines | |
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* | ecp5: Delay tweaking for lower speed grades | David Shah | 2019-06-21 | 1 | -2/+4 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Reduce cfg.criticalityExponent for now | David Shah | 2019-06-21 | 1 | -1/+1 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | Add --placer option and refactor placer selection | David Shah | 2019-03-24 | 1 | -9/+21 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Speedup cell delay lookups | David Shah | 2019-03-22 | 1 | -1/+7 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | HeAP: Add PlacerHeapCfg | David Shah | 2019-03-22 | 1 | -2/+5 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | HeAP: Make HeAP placer optional | David Shah | 2019-03-22 | 1 | -1/+18 |
| | | | | | | | | | | | | | A CMake option 'BUILD_HEAP' (default on) configures building of the HeAP placer and the associated Eigen3 dependency. Default for the iCE40 is SA placer, with --heap-placer to use HeAP Default for the ECP5 is HeAP placer, as SA placer can take 1hr+ for large ECP5 designs and HeAP tends to give better QoR. --sa-placer can be used to use SA instead, and auto-fallback to SA if HeAP not built. Signed-off-by: David Shah <dave@ds0.me> | ||||
* | HeAP: tidying up | David Shah | 2019-03-22 | 1 | -1/+1 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | HeAP: Use for ECP5 as well as iCE40 | David Shah | 2019-03-22 | 1 | -7/+2 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | HeAP: Add TAUCS wrapper and integration | David Shah | 2019-03-22 | 1 | -1/+1 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: DELAY fixes | David Shah | 2019-02-25 | 1 | -5/+1 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Improve packing density | David Shah | 2019-02-25 | 1 | -1/+1 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Add criticality-based LUT permutation | David Shah | 2019-02-25 | 1 | -1/+11 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Delay tuning | David Shah | 2019-02-25 | 1 | -18/+31 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Fix global clock routing with multiclock DPRAM | David Shah | 2019-02-25 | 1 | -3/+6 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Router performance improvements | David Shah | 2019-02-25 | 1 | -4/+17 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Implement budget overrides for carry chains and SLICE muxes | David Shah | 2019-02-25 | 1 | -2/+12 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Improve delay model | David Shah | 2019-02-25 | 1 | -3/+4 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Speed up timing analysis | David Shah | 2019-02-25 | 1 | -4/+3 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Add ECLKSYNCB support | David Shah | 2019-02-24 | 1 | -0/+4 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Packing of ODDRX2F | David Shah | 2019-02-24 | 1 | -0/+2 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Helper functions for DQS and ECLK | David Shah | 2019-02-24 | 1 | -0/+37 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Add timing data for DQS-related cells | David Shah | 2019-02-24 | 1 | -0/+27 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | Merge branch 'master' into mmaped_chipdb | Miodrag Milanović | 2019-02-12 | 1 | -1/+22 |
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| * | ecp5: Fix global routing performance | David Shah | 2019-02-12 | 1 | -1/+22 |
| | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | Load chipdb from filesystem as option | Miodrag Milanovic | 2019-02-09 | 1 | -1/+28 |
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* | ecp5: Adding DTR, OSCG, CLKDIVF, USRMCLK, JTAGG | David Shah | 2019-02-08 | 1 | -0/+17 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Add IOLOGIC timing and bitstream; ODDR working | David Shah | 2018-12-14 | 1 | -0/+20 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | Improve reporting of unknown cell types | David Shah | 2018-11-29 | 1 | -1/+2 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Adding mux support up to LUT6 | David Shah | 2018-11-16 | 1 | -1/+2 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: clangformat timing changes | David Shah | 2018-11-16 | 1 | -1/+1 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Use speed-grade-specific delay estimate | David Shah | 2018-11-16 | 1 | -2/+2 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Fix db import, improve timing data debugging | David Shah | 2018-11-16 | 1 | -1/+28 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Post-rebase fix | David Shah | 2018-11-16 | 1 | -3/+3 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Use new timing data | David Shah | 2018-11-16 | 1 | -77/+59 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Adding real timing data to database | David Shah | 2018-11-16 | 1 | -1/+1 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Add timing info for SERDES | David Shah | 2018-11-15 | 1 | -1/+26 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Adding ancillary DCU bels | David Shah | 2018-11-15 | 1 | -1/+1 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Working on DCU | David Shah | 2018-11-15 | 1 | -0/+2 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | Merge remote-tracking branch 'origin/master' into timingapi | Eddie Hung | 2018-11-13 | 1 | -2/+2 |
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| * | Merge pull request #107 from YosysHQ/router_improve | Eddie Hung | 2018-11-13 | 1 | -2/+2 |
| |\ | | | | | | | Major rewrite of "router1" | ||||
| | * | ecp5: Improve delay estimates | David Shah | 2018-11-13 | 1 | -2/+2 |
| | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | | ecp5: EBR clocking fix | David Shah | 2018-11-12 | 1 | -5/+8 |
| | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | | | ecp5: Update arch to new timing API | David Shah | 2018-11-12 | 1 | -13/+62 |
|/ / | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* / | show 4th tresllis_io in tile bounds | Miodrag Milanovic | 2018-11-11 | 1 | -1/+1 |
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* | ecp5: Add PLL support | David Shah | 2018-10-31 | 1 | -0/+2 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Adding DSP support | David Shah | 2018-10-21 | 1 | -0/+4 |
| | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | ecp5: Implement ECP5 equivalent of c9059fc | David Shah | 2018-10-21 | 1 | -0/+9 |
| | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | clangformat | David Shah | 2018-10-16 | 1 | -2/+4 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Add support for correct tile naming in all variants | David Shah | 2018-10-16 | 1 | -3/+27 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> | ||||
* | ecp5: Add DP16KD timing analysis | David Shah | 2018-10-16 | 1 | -2/+29 |
| | | | | Signed-off-by: David Shah <dave@ds0.me> |