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* archapi: Use arbitrary rather than actual placement in predictDelaygatecat2021-12-191-1/+1
* ecp5: LUT permutation supportgatecat2021-12-131-2/+48
* ecp5: Reduce some chipdb fields sizesMatt Johnston2021-12-131-6/+5
* clangformatgatecat2021-12-121-4/+6
* ecp5: Use a vector rather than dictMatt Johnston2021-12-121-14/+83
* Fixing old emails and names in copyrightsgatecat2021-06-121-2/+2
* Using hashlib in archesgatecat2021-06-021-20/+6
* Split nextpnr.h to allow for linear inclusion.Keith Rothman2021-03-151-5/+8
* Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-191-24/+11
* Remove isValidBelForCellgatecat2021-02-161-1/+0
* Add getBelHidden and add some missing "override" statements.Keith Rothman2021-02-111-1/+1
* Add BaseArchRanges for default ArchRanges typesgatecat2021-02-091-16/+1
* Merge pull request #568 from YosysHQ/dave/arch-overridegatecat2021-02-081-226/+113
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| * Use 'T' postfix to disambiguate LHS and RHS of usingD. Shah2021-02-081-21/+21
| * Add archArgs and archArgsToId to Arch APID. Shah2021-02-051-2/+3
| * Rename ArchBase to BaseArch for consistency with BaseCtxD. Shah2021-02-051-4/+4
| * Add default implementation of bel bucket functionsD. Shah2021-02-051-41/+2
| * Add default implementation of some range-returning functionsD. Shah2021-02-051-12/+0
| * Add a few more functions to ArchBaseD. Shah2021-02-051-3/+4
| * ecp5: Use common wire/pip bindingD. Shah2021-02-051-82/+6
| * nextpnr: Use templates to specify range typesD. Shah2021-02-051-18/+46
| * nextpnr: Add base virtual functions for non-range Arch APID. Shah2021-02-051-84/+68
* | Use RelSlice::ssize instead of cast-to-int throughoutD. Shah2021-02-081-4/+4
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* ecp5: Use snake case for arch-specific functionsD. Shah2021-02-031-62/+62
* ecp5: Implement IdStringList for all arch object namesD. Shah2021-02-021-14/+12
* ecp5: Proof-of-concept using IdStringList for bel namesD. Shah2021-02-021-5/+8
* arch: Add getNameDelimiter API for string listsD. Shah2021-02-021-0/+1
* Run "make clangformat".Keith Rothman2021-02-021-18/+14
* Rename Partition -> BelBucket.Keith Rothman2021-02-021-19/+19
* Refactor ECP5 to new Partition API.Keith Rothman2021-02-021-0/+44
* Initial refactoring of placer API.Keith Rothman2021-02-021-0/+3
* Move RelPtr/RelSlice out of arches into commonD. Shah2021-01-271-37/+1
* ecp5: Switch from RelPtr to RelSliceD. Shah2021-01-271-61/+62
* RelPtr: remove copy constructor and copy assignmentDavid Shah2020-11-131-0/+3
* Remove wire alias APIDavid Shah2020-10-151-9/+0
* ecp5: Fix getTileBelDimZDavid Shah2020-06-291-2/+3
* Simplify and improve chipdb embedding/loading.whitequark2020-06-261-10/+3
* CMake: rewrite chipdb handling from ground up.whitequark2020-06-251-1/+1
* ecp5: Proper support for '12k' deviceDavid Shah2020-03-131-0/+1
* Allow selection of router algorithmDavid Shah2020-02-031-0/+2
* ecp5: Router2 test integrationDavid Shah2020-02-031-0/+1
* Merge remote-tracking branch 'origin/master' into mmicko/ecp5_guiMiodrag Milanovic2019-12-281-1/+7
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| * ecp5: Fix 25k DDRDLLA bitstream genDavid Shah2019-11-291-1/+1
| * ecp5: Add an error for out-of-sync constids and bbaDavid Shah2019-10-261-0/+1
| * ecp5: Fix routing to shared DSP control inputsDavid Shah2019-10-251-0/+5
* | set wire active flagMiodrag Milanovic2019-10-201-0/+2
* | Start adding visible wiresMiodrag Milanovic2019-10-201-5/+2
* | Added type to wireMiodrag Milanovic2019-10-201-1/+8
* | Draw swbox, smaller slices, proper ioMiodrag Milanovic2019-10-201-7/+7
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* ecp5: Add full part name to bitstream headerDavid Shah2019-08-271-0/+1
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