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path: root/ecp5/archdefs.h
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* ecp5: Split the SLICE bel into separate LUT/FF/RAMW belsgatecat2022-04-071-7/+34
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* ecp5: LUT permutation supportgatecat2021-12-131-0/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: Use a vector rather than dictMatt Johnston2021-12-121-0/+2
| | | | | This improves router1 performance vs the default dict Using it for wire2net, pip2net, wire_fanout
* Fixing old emails and names in copyrightsgatecat2021-06-121-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Remove redundant code after hashlib movegatecat2021-06-021-70/+0
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add hash() member functionsgatecat2021-06-021-0/+7
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: Use new cluster APIgatecat2021-05-061-1/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Split nextpnr.h to allow for linear inclusion.Keith Rothman2021-03-151-5/+9
| | | | | | | | | | | | | | | | | | | "nextpnr.h" is no longer the god header. Important improvements: - Functions in log.h can be used without including BaseCtx/Arch/Context. This means that log_X functions can be called without included "nextpnr.h" - NPNR_ASSERT can be used without including "nextpnr.h" by including "nextpnr_assertions.h". This allows NPNR_ASSERT to be used safely in any header file. - Types defined in "archdefs.h" are now available without including BaseCtx/Arch/Context. This means that utility classes that will be used inside of BaseCtx/Arch/Context can be defined safely in a self-contained header. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Fix compiler warnings introduced by -Wextragatecat2021-02-251-1/+0
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-191-22/+0
| | | | | | | | | | | | | | | | | This replaces the arch-specific DelayInfo structure with new DelayPair (min/max only) and DelayQuad (min/max for both rise and fall) structures that form part of common code. This further reduces the amount of arch-specific code; and also provides useful data structures for timing analysis which will need to delay with pairs/quads of delays as it is improved. While there may be a small performance cost to arches that didn't separate the rise/fall cases (arches that aren't currently separating the min/max cases just need to be fixed...) in DelayInfo, my expectation is that inlining will mean this doesn't make much difference. Signed-off-by: gatecat <gatecat@ds0.me>
* Add default implementation of bel bucket functionsD. Shah2021-02-051-18/+1
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* Run "make clangformat".Keith Rothman2021-02-021-5/+3
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Rename Partition -> BelBucket.Keith Rothman2021-02-021-6/+6
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Working compile of ECP5.Keith Rothman2021-02-021-0/+14
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Refactor ECP5 to new Partition API.Keith Rothman2021-02-021-0/+7
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Issue warning for mixed-mode inputsRoss Schlaikjer2020-04-291-3/+1
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* Alter MULT18X18D timing db based on register configRoss Schlaikjer2020-04-281-1/+7
| | | | | | | | | | | | | | | If the REG_INPUTA_CLK and REG_INPUTB_CLK values are set, then we should use the faster setup/hold timings for the 18x8 multiplier. Similarly, check the value of REG_OUTPUT_CLK for whether or not to use faster timings for the output. This is based on how I currently understand the registers to work - if anyone knows the actual rules for when each timing applies please do chime in to correct this implementation if necessary. Along the same lines, this PR does not address the case when the pipeline registers are enabled, since it is not clear to me how exactly that affects the timing.
* Actually just move all the logic to ArchInfoRoss Schlaikjer2020-04-071-2/+8
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* Extract regmode configuration to ArchInfoRoss Schlaikjer2020-04-071-0/+2
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* Merge remote-tracking branch 'origin/master' into mmicko/ecp5_guiMiodrag Milanovic2019-12-281-0/+6
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| * Work around Qt MOC issue with IdString enumsDavid Shah2019-12-271-0/+4
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * ecp5: Add an error for out-of-sync constids and bbaDavid Shah2019-10-261-0/+2
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | type needs to be part of hash for GroupIdMiodrag Milanovic2019-10-201-1/+3
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* | Draw swbox, smaller slices, proper ioMiodrag Milanovic2019-10-201-6/+15
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* ecp5: Adding support for 36-bit wide PDP RAMsDavid Shah2019-10-011-0/+4
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Speed up timing analysisDavid Shah2019-02-251-0/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: More optimal LUT6 placementDavid Shah2018-11-161-0/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Adding real timing data to databaseDavid Shah2018-11-161-8/+9
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Regression fix & formatDavid Shah2018-11-151-3/+12
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Various router1 fixes, Add BelId/WireId/PipId::operator<()Clifford Wolf2018-11-131-0/+4
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* ecp5: Improve mixed no-FF/FF placementDavid Shah2018-09-301-0/+1
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Use ArchNetInfo to mark global nets to ignoreDavid Shah2018-09-291-0/+2
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Speedup placement using ArchCellInfoDavid Shah2018-08-181-0/+4
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Update to use const IdStrings in place of PortPin/BelTypeDavid Shah2018-08-081-18/+7
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Remove getFrameDecal() APIClifford Wolf2018-08-011-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* ecp5: Add Bel graphicsDavid Shah2018-07-311-4/+9
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Change DelayInfo semantics to what we actually needClifford Wolf2018-07-211-3/+8
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* ecp5: Add simple constant packerDavid Shah2018-07-181-2/+6
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Add ArchNetInfo and ArchCellInfoClifford Wolf2018-07-171-0/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fixing hash link problemDavid Shah2018-07-131-1/+1
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Updates from clang-formatClifford Wolf2018-07-121-2/+8
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add Groups APIClifford Wolf2018-07-121-0/+19
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* ecp5: Update arch to use new graphics APIDavid Shah2018-07-111-0/+21
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Fixing arch bugsDavid Shah2018-07-111-1/+1
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Implementing (at least stubs) most of arch.ccDavid Shah2018-07-111-1/+1
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Implementing core arch.h functionsDavid Shah2018-07-111-8/+38
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Working on arch implementationDavid Shah2018-07-111-4/+4
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Begin planning data structuresDavid Shah2018-07-111-0/+126
Signed-off-by: David Shah <davey1576@gmail.com>
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