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* Add remapping of DSP clk/ce/rst signals in a block.Adam Greig2023-01-041-0/+17
| | | | | | | | | | | | | | | | | | Each DSP block contains two slices, and each slice contains multiple MULT18X18D and ALU54B units. Each unit configures each register to use any of CLK0/1/2/3, CE0/1/2/3, and RST0/1/2/3 ports, and the ports are connected per unit (so for example, two MULTs in the same block could connect their CLK0s to different external signals). However, the hardware only has one actual port per block, so it's required that all CLK0 signals within a block are the same. Because the packer is in general allowed to combine two unrelated units into one block, it may end up combining units that use different signals for the same port, which would eventually have caused a router failure. This commit adds validity checks which ensure only unique signals are used per block, and adds remapping so that conflicting signals are automatically reassigned when possible and required.
* ecp5: Split the SLICE bel into separate LUT/FF/RAMW belsgatecat2022-04-071-0/+10
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* refactor: Use constids instead of id("..")gatecat2022-02-161-0/+510
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* ecp5: Add DCSC supportgatecat2021-07-061-0/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge remote-tracking branch 'origin/master' into mmicko/ecp5_guiMiodrag Milanovic2019-12-281-0/+8
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| * ecp5: Add constids for new timing cell typesDavid Shah2019-10-261-0/+8
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | add newline at eofMiodrag Milanovic2019-12-281-1/+1
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* | Add global wiresMiodrag Milanovic2019-12-151-1/+4
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* | more new wires addedMiodrag Milanovic2019-12-141-0/+7
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* | new wires in dbMiodrag Milanovic2019-12-131-1/+5
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* | added siologicMiodrag Milanovic2019-12-131-0/+1
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* | Add many new wiresMiodrag Milanovic2019-12-131-0/+7
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* | display horizontal wires, add some globals to listMiodrag Milanovic2019-10-231-0/+2
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* | Simplify layout of elementsMiodrag Milanovic2019-10-201-2/+0
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* | more wires between switchboxesMiodrag Milanovic2019-10-201-0/+2
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* | Less types neededMiodrag Milanovic2019-10-201-16/+8
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* | Added type to wireMiodrag Milanovic2019-10-201-0/+19
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* ecp5: Add IDDR71B supportDavid Shah2019-10-091-0/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Preparations for new IO belsDavid Shah2019-10-091-1/+5
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Conservative analysis of comb DSP timingDavid Shah2019-07-081-1/+8
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Helper functions for DQS and ECLKDavid Shah2019-02-241-0/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Adding DTR, OSCG, CLKDIVF, USRMCLK, JTAGGDavid Shah2019-02-081-1/+99
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add {S}IOLOGIC constids and cellDavid Shah2018-12-121-0/+40
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Adding real timing data to databaseDavid Shah2018-11-161-2/+27
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Adding ancillary DCU belsDavid Shah2018-11-151-0/+7
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Groundwork for DCU supportDavid Shah2018-11-151-0/+300
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add PLL supportDavid Shah2018-10-311-0/+23
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Adding DSP supportDavid Shah2018-10-211-1/+616
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Adding constids for blockramDavid Shah2018-10-051-0/+118
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ecp5: Add DCC Bels, fix global router post-rebaseDavid Shah2018-09-291-0/+4
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ecp5: Update to use const IdStrings in place of PortPin/BelTypeDavid Shah2018-08-081-0/+52
Signed-off-by: David Shah <davey1576@gmail.com>
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