refactor: Use constids instead of id("..")

Signed-off-by: gatecat <gatecat@ds0.me>

1 files changed, 510 insertions, 0 deletions

diff --git a/ecp5/constids.inc b/ecp5/constids.inc
index 335f822a..760e1623 100644
--- a/ecp5/constids.inc
+++ b/ecp5/constids.inc
@@ -1341,3 +1341,513 @@ X(IOLOGIC_MODE_TSREG)
 X(DCSC)
 X(DCSOUT)
 X(MODESEL)
+
+X(ALUT)
+X(ASYNC_RESET_RELEASE)
+X(BEL)
+X(BLUT)
+X(C)
+X(CCU2C)
+X(CCU2_INJECT1_0)
+X(CCU2_INJECT1_1)
+X(CEAMUX)
+X(CEBMUX)
+X(CEIMUX)
+X(CEMUX)
+X(CEOMUX)
+X(CER)
+X(CEW)
+X(CH0_AUTO_CALIB_EN)
+X(CH0_AUTO_FACQ_EN)
+X(CH0_BAND_THRESHOLD)
+X(CH0_CALIB_CK_MODE)
+X(CH0_CC_MATCH_1)
+X(CH0_CC_MATCH_2)
+X(CH0_CC_MATCH_3)
+X(CH0_CC_MATCH_4)
+X(CH0_CDR_CNT4SEL)
+X(CH0_CDR_CNT8SEL)
+X(CH0_CTC_BYPASS)
+X(CH0_DCOATDCFG)
+X(CH0_DCOATDDLY)
+X(CH0_DCOBYPSATD)
+X(CH0_DCOCALDIV)
+X(CH0_DCOCTLGI)
+X(CH0_DCODISBDAVOID)
+X(CH0_DCOFLTDAC)
+X(CH0_DCOFTNRG)
+X(CH0_DCOIOSTUNE)
+X(CH0_DCOITUNE)
+X(CH0_DCOITUNE4LSB)
+X(CH0_DCOIUPDNX2)
+X(CH0_DCONUOFLSB)
+X(CH0_DCOSCALEI)
+X(CH0_DCOSTARTVAL)
+X(CH0_DCOSTEP)
+X(CH0_DEC_BYPASS)
+X(CH0_ENABLE_CG_ALIGN)
+X(CH0_ENC_BYPASS)
+X(CH0_FF_RX_F_CLK_DIS)
+X(CH0_FF_RX_H_CLK_EN)
+X(CH0_FF_TX_F_CLK_DIS)
+X(CH0_FF_TX_H_CLK_EN)
+X(CH0_GE_AN_ENABLE)
+X(CH0_INVERT_RX)
+X(CH0_INVERT_TX)
+X(CH0_LDR_CORE2TX_SEL)
+X(CH0_LDR_RX2CORE_SEL)
+X(CH0_LEQ_OFFSET_SEL)
+X(CH0_LEQ_OFFSET_TRIM)
+X(CH0_LSM_DISABLE)
+X(CH0_MATCH_2_ENABLE)
+X(CH0_MATCH_4_ENABLE)
+X(CH0_MIN_IPG_CNT)
+X(CH0_PCIE_EI_EN)
+X(CH0_PCIE_MODE)
+X(CH0_PCS_DET_TIME_SEL)
+X(CH0_PDEN_SEL)
+X(CH0_PRBS_ENABLE)
+X(CH0_PRBS_LOCK)
+X(CH0_PRBS_SELECTION)
+X(CH0_RATE_MODE_RX)
+X(CH0_RATE_MODE_TX)
+X(CH0_RCV_DCC_EN)
+X(CH0_REG_BAND_OFFSET)
+X(CH0_REG_BAND_SEL)
+X(CH0_REG_IDAC_EN)
+X(CH0_REG_IDAC_SEL)
+X(CH0_REQ_EN)
+X(CH0_REQ_LVL_SET)
+X(CH0_RIO_MODE)
+X(CH0_RLOS_SEL)
+X(CH0_RPWDNB)
+X(CH0_RTERM_RX)
+X(CH0_RTERM_TX)
+X(CH0_RXIN_CM)
+X(CH0_RXTERM_CM)
+X(CH0_RX_DCO_CK_DIV)
+X(CH0_RX_DIV11_SEL)
+X(CH0_RX_GEAR_BYPASS)
+X(CH0_RX_GEAR_MODE)
+X(CH0_RX_LOS_CEQ)
+X(CH0_RX_LOS_EN)
+X(CH0_RX_LOS_HYST_EN)
+X(CH0_RX_LOS_LVL)
+X(CH0_RX_RATE_SEL)
+X(CH0_RX_SB_BYPASS)
+X(CH0_SB_BYPASS)
+X(CH0_SEL_SD_RX_CLK)
+X(CH0_TDRV_DAT_SEL)
+X(CH0_TDRV_POST_EN)
+X(CH0_TDRV_PRE_EN)
+X(CH0_TDRV_SLICE0_CUR)
+X(CH0_TDRV_SLICE0_SEL)
+X(CH0_TDRV_SLICE1_CUR)
+X(CH0_TDRV_SLICE1_SEL)
+X(CH0_TDRV_SLICE2_CUR)
+X(CH0_TDRV_SLICE2_SEL)
+X(CH0_TDRV_SLICE3_CUR)
+X(CH0_TDRV_SLICE3_SEL)
+X(CH0_TDRV_SLICE4_CUR)
+X(CH0_TDRV_SLICE4_SEL)
+X(CH0_TDRV_SLICE5_CUR)
+X(CH0_TDRV_SLICE5_SEL)
+X(CH0_TPWDNB)
+X(CH0_TX_CM_SEL)
+X(CH0_TX_DIV11_SEL)
+X(CH0_TX_GEAR_BYPASS)
+X(CH0_TX_GEAR_MODE)
+X(CH0_TX_POST_SIGN)
+X(CH0_TX_PRE_SIGN)
+X(CH0_UC_MODE)
+X(CH0_UDF_COMMA_A)
+X(CH0_UDF_COMMA_B)
+X(CH0_UDF_COMMA_MASK)
+X(CH0_WA_BYPASS)
+X(CH0_WA_MODE)
+X(CH1_AUTO_CALIB_EN)
+X(CH1_AUTO_FACQ_EN)
+X(CH1_BAND_THRESHOLD)
+X(CH1_CALIB_CK_MODE)
+X(CH1_CC_MATCH_1)
+X(CH1_CC_MATCH_2)
+X(CH1_CC_MATCH_3)
+X(CH1_CC_MATCH_4)
+X(CH1_CDR_CNT4SEL)
+X(CH1_CDR_CNT8SEL)
+X(CH1_CTC_BYPASS)
+X(CH1_DCOATDCFG)
+X(CH1_DCOATDDLY)
+X(CH1_DCOBYPSATD)
+X(CH1_DCOCALDIV)
+X(CH1_DCOCTLGI)
+X(CH1_DCODISBDAVOID)
+X(CH1_DCOFLTDAC)
+X(CH1_DCOFTNRG)
+X(CH1_DCOIOSTUNE)
+X(CH1_DCOITUNE)
+X(CH1_DCOITUNE4LSB)
+X(CH1_DCOIUPDNX2)
+X(CH1_DCONUOFLSB)
+X(CH1_DCOSCALEI)
+X(CH1_DCOSTARTVAL)
+X(CH1_DCOSTEP)
+X(CH1_DEC_BYPASS)
+X(CH1_ENABLE_CG_ALIGN)
+X(CH1_ENC_BYPASS)
+X(CH1_FF_RX_F_CLK_DIS)
+X(CH1_FF_RX_H_CLK_EN)
+X(CH1_FF_TX_F_CLK_DIS)
+X(CH1_FF_TX_H_CLK_EN)
+X(CH1_GE_AN_ENABLE)
+X(CH1_INVERT_RX)
+X(CH1_INVERT_TX)
+X(CH1_LDR_CORE2TX_SEL)
+X(CH1_LDR_RX2CORE_SEL)
+X(CH1_LEQ_OFFSET_SEL)
+X(CH1_LEQ_OFFSET_TRIM)
+X(CH1_LSM_DISABLE)
+X(CH1_MATCH_2_ENABLE)
+X(CH1_MATCH_4_ENABLE)
+X(CH1_MIN_IPG_CNT)
+X(CH1_PCIE_EI_EN)
+X(CH1_PCIE_MODE)
+X(CH1_PCS_DET_TIME_SEL)
+X(CH1_PDEN_SEL)
+X(CH1_PRBS_ENABLE)
+X(CH1_PRBS_LOCK)
+X(CH1_PRBS_SELECTION)
+X(CH1_RATE_MODE_RX)
+X(CH1_RATE_MODE_TX)
+X(CH1_RCV_DCC_EN)
+X(CH1_REG_BAND_OFFSET)
+X(CH1_REG_BAND_SEL)
+X(CH1_REG_IDAC_EN)
+X(CH1_REG_IDAC_SEL)
+X(CH1_REQ_EN)
+X(CH1_REQ_LVL_SET)
+X(CH1_RIO_MODE)
+X(CH1_RLOS_SEL)
+X(CH1_RPWDNB)
+X(CH1_RTERM_RX)
+X(CH1_RTERM_TX)
+X(CH1_RXIN_CM)
+X(CH1_RXTERM_CM)
+X(CH1_RX_DCO_CK_DIV)
+X(CH1_RX_DIV11_SEL)
+X(CH1_RX_GEAR_BYPASS)
+X(CH1_RX_GEAR_MODE)
+X(CH1_RX_LOS_CEQ)
+X(CH1_RX_LOS_EN)
+X(CH1_RX_LOS_HYST_EN)
+X(CH1_RX_LOS_LVL)
+X(CH1_RX_RATE_SEL)
+X(CH1_RX_SB_BYPASS)
+X(CH1_SB_BYPASS)
+X(CH1_SEL_SD_RX_CLK)
+X(CH1_TDRV_DAT_SEL)
+X(CH1_TDRV_POST_EN)
+X(CH1_TDRV_PRE_EN)
+X(CH1_TDRV_SLICE0_CUR)
+X(CH1_TDRV_SLICE0_SEL)
+X(CH1_TDRV_SLICE1_CUR)
+X(CH1_TDRV_SLICE1_SEL)
+X(CH1_TDRV_SLICE2_CUR)
+X(CH1_TDRV_SLICE2_SEL)
+X(CH1_TDRV_SLICE3_CUR)
+X(CH1_TDRV_SLICE3_SEL)
+X(CH1_TDRV_SLICE4_CUR)
+X(CH1_TDRV_SLICE4_SEL)
+X(CH1_TDRV_SLICE5_CUR)
+X(CH1_TDRV_SLICE5_SEL)
+X(CH1_TPWDNB)
+X(CH1_TX_CM_SEL)
+X(CH1_TX_DIV11_SEL)
+X(CH1_TX_GEAR_BYPASS)
+X(CH1_TX_GEAR_MODE)
+X(CH1_TX_POST_SIGN)
+X(CH1_TX_PRE_SIGN)
+X(CH1_UC_MODE)
+X(CH1_UDF_COMMA_A)
+X(CH1_UDF_COMMA_B)
+X(CH1_UDF_COMMA_MASK)
+X(CH1_WA_BYPASS)
+X(CH1_WA_MODE)
+X(CIN)
+X(CLAMP)
+X(CLK0_DIV)
+X(CLK1_DIV)
+X(CLK2_DIV)
+X(CLK3_DIV)
+X(CLKAMUX)
+X(CLKBMUX)
+X(CLKFB_DIV)
+X(CLKIMUX)
+X(CLKI_DIV)
+X(CLKOMUX)
+X(CLKOP_DIV)
+X(CLKOP_ENABLE)
+X(CLKOP_TRIM_DELAY)
+X(CLKOP_TRIM_POL)
+X(CLKOS2_DIV)
+X(CLKOS2_ENABLE)
+X(CLKOS3_DIV)
+X(CLKOS3_ENABLE)
+X(CLKOS_DIV)
+X(CLKOS_ENABLE)
+X(CLKOS_TRIM_DELAY)
+X(CLKOS_TRIM_POL)
+X(CLKR)
+X(CLKW)
+X(COUT)
+X(CSDECODE_A)
+X(CSDECODE_B)
+X(D)
+X(D2)
+X(D3)
+X(D4)
+X(D5)
+X(D6)
+X(DATAMUX_MDDR)
+X(DATAMUX_ODDR)
+X(DATAMUX_OREG)
+X(DATA_WIDTH_A)
+X(DATA_WIDTH_B)
+X(DATA_WIDTH_W)
+X(DCSMODE)
+X(DDRDLLA)
+X(DELAYF)
+X(DELAYG)
+X(DEL_MODE)
+X(DEL_VALUE)
+X(DIFFRESISTOR)
+X(DIR)
+X(DIV)
+X(DPHASE_SOURCE)
+X(DQS_LI_DEL_ADJ)
+X(DQS_LI_DEL_VAL)
+X(DQS_LO_DEL_ADJ)
+X(DQS_LO_DEL_VAL)
+X(DRIVE)
+X(D_BITCLK_FROM_ND_EN)
+X(D_BITCLK_LOCAL_EN)
+X(D_BITCLK_ND_EN)
+X(D_BUS8BIT_SEL)
+X(D_CDR_LOL_SET)
+X(D_CMUSETBIASI)
+X(D_CMUSETI4CPP)
+X(D_CMUSETI4CPZ)
+X(D_CMUSETI4VCO)
+X(D_CMUSETICP4P)
+X(D_CMUSETICP4Z)
+X(D_CMUSETINITVCT)
+X(D_CMUSETISCL4VCO)
+X(D_CMUSETP1GM)
+X(D_CMUSETP2AGM)
+X(D_CMUSETZGM)
+X(D_DCO_CALIB_TIME_SEL)
+X(D_HIGH_MARK)
+X(D_IB_PWDNB)
+X(D_ISETLOS)
+X(D_LOW_MARK)
+X(D_MACROPDB)
+X(D_PD_ISET)
+X(D_PLL_LOL_SET)
+X(D_REFCK_MODE)
+X(D_REQ_ISET)
+X(D_RG_EN)
+X(D_RG_SET)
+X(D_SETICONST_AUX)
+X(D_SETICONST_CH)
+X(D_SETIRPOLY_AUX)
+X(D_SETIRPOLY_CH)
+X(D_SETPLLRC)
+X(D_SYNC_LOCAL_EN)
+X(D_SYNC_ND_EN)
+X(D_TXPLL_PWDNB)
+X(D_TX_VCO_CK_DIV)
+X(D_XGE_MODE)
+X(E)
+X(ECP5_IS_GLOBAL)
+X(ER1)
+X(ER2)
+X(FEEDBK_PATH)
+X(FORCE_MAX_DELAY)
+X(FORCE_ZERO_BARREL_SHIFT)
+X(FREQ_LOCK_ACCURACY)
+X(GND)
+X(HYSTERESIS)
+X(ICP_CURRENT)
+X(IDDR71B)
+X(IDDRX1F)
+X(IDDRX2DQA)
+X(IDDRX2F)
+X(INIT)
+X(INIT0)
+X(INIT1)
+X(INITVAL)
+X(INJECT1_0)
+X(INJECT1_1)
+X(INTFB_WAKE)
+X(INT_LOCK_STICKY)
+X(INV)
+X(IOLTOMUX)
+X(IO_TYPE)
+X(KVCO)
+X(L6MUX21)
+X(LEGACY)
+X(LOC)
+X(LPF_CAPACITOR)
+X(LPF_RESISTOR)
+X(LSRIMUX)
+X(LSRMODE)
+X(LSROMUX)
+X(LUT0_INITVAL)
+X(LUT1_INITVAL)
+X(LUT4)
+X(M)
+X(MASK01)
+X(MASKPAT)
+X(MASKPAT_SOURCE)
+X(MCPAT)
+X(MCPAT_SOURCE)
+X(MFG1_TEST)
+X(MFG2_TEST)
+X(MFG_ENABLE_FILTEROPAMP)
+X(MFG_EN_UP)
+X(MFG_FLOAT_ICP)
+X(MFG_FORCE_VFILTER)
+X(MFG_GMCREF_SEL)
+X(MFG_GMC_GAIN)
+X(MFG_GMC_PRESET)
+X(MFG_GMC_RESET)
+X(MFG_GMC_TEST)
+X(MFG_ICP_TEST)
+X(MFG_LF_PRESET)
+X(MFG_LF_RESET)
+X(MFG_LF_RESGRND)
+X(MODE)
+X(MULT_BYPASS)
+X(OCEAMUX)
+X(OCEBMUX)
+X(OCER)
+X(ODDR71B)
+X(ODDRX1F)
+X(ODDRX2DQA)
+X(ODDRX2DQSB)
+X(ODDRX2F)
+X(OPENDRAIN)
+X(OSHX2A)
+X(OUTDIVIDER_MUXA)
+X(OUTDIVIDER_MUXB)
+X(OUTDIVIDER_MUXC)
+X(OUTDIVIDER_MUXD)
+X(PDPW16KD)
+X(PFUMX)
+X(PLLRST_ENA)
+X(PLL_LOCK_MODE)
+X(PULLMODE)
+X(Q)
+X(Q2)
+X(Q3)
+X(Q4)
+X(Q5)
+X(Q6)
+X(QWL)
+X(REFCK_DCBIAS_EN)
+X(REFCK_PWDNB)
+X(REFCK_RTERM)
+X(REFIN_RESET)
+X(REG0_LSRMODE)
+X(REG0_REGSET)
+X(REG0_SD)
+X(REG1_LSRMODE)
+X(REG1_REGSET)
+X(REG1_SD)
+X(REGMODE)
+X(REGMODE_A)
+X(REGMODE_B)
+X(REGSET)
+X(REG_FLAG_CLK)
+X(REG_INPUTA_CE)
+X(REG_INPUTA_CLK)
+X(REG_INPUTA_RST)
+X(REG_INPUTB_CE)
+X(REG_INPUTB_CLK)
+X(REG_INPUTB_RST)
+X(REG_INPUTC0_CLK)
+X(REG_INPUTC1_CLK)
+X(REG_INPUTC_CLK)
+X(REG_OPCODEIN_0_CE)
+X(REG_OPCODEIN_0_CLK)
+X(REG_OPCODEIN_0_RST)
+X(REG_OPCODEIN_1_CE)
+X(REG_OPCODEIN_1_CLK)
+X(REG_OPCODEIN_1_RST)
+X(REG_OPCODEOP0_0_CE)
+X(REG_OPCODEOP0_0_CLK)
+X(REG_OPCODEOP0_0_RST)
+X(REG_OPCODEOP0_1_CE)
+X(REG_OPCODEOP0_1_CLK)
+X(REG_OPCODEOP0_1_RST)
+X(REG_OPCODEOP1_0_CLK)
+X(REG_OPCODEOP1_1_CLK)
+X(REG_OUTPUT0_CLK)
+X(REG_OUTPUT1_CLK)
+X(REG_OUTPUT_CLK)
+X(REG_OUTPUT_RST)
+X(REG_PIPELINE_CE)
+X(REG_PIPELINE_CLK)
+X(REG_PIPELINE_RST)
+X(RESETMODE)
+X(RNDPAT)
+X(RSTAMUX)
+X(RSTBMUX)
+X(S0)
+X(S1)
+X(SD)
+X(SGSR)
+X(SLEWRATE)
+X(SOURCEB_MODE)
+X(STDBY_ENABLE)
+X(SYNCMODE)
+X(SYNC_ENABLE)
+X(T0)
+X(T1)
+X(TERMINATION)
+X(TILE_WIRE_ID)
+X(TRELLIS_DPR16X4)
+X(TRELLIS_FF)
+X(TRIMUX_TSREG)
+X(TSHX2DQA)
+X(TSHX2DQSA)
+X(USRMCLKI)
+X(USRMCLKO)
+X(USRMCLKTS)
+X(VCC)
+X(WCKMUX)
+X(WEAMUX)
+X(WEBMUX)
+X(WID)
+X(WREMUX)
+X(WRITEMODE_A)
+X(WRITEMODE_B)
+X(Y)
+X(ioff_dir)
+X(lfe5u_12f)
+X(lfe5u_25f)
+X(lfe5u_45f)
+X(lfe5u_85f)
+X(lfe5um5g_25f)
+X(lfe5um5g_45f)
+X(lfe5um5g_85f)
+X(lfe5um_25f)
+X(lfe5um_45f)
+X(lfe5um_85f)
+X(noglobal)
+X(pack)
+X(place)
+X(placer)
+X(route)
+X(router)
+X(syn_useioff)