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| | * | ecp5: Improve delay estimatesDavid Shah2018-11-131-2/+2
| | * | Various router1 fixes, Add BelId/WireId/PipId::operator<()Clifford Wolf2018-11-131-0/+4
| | * | clangformatClifford Wolf2018-11-111-8/+2
| | * | Add getConflictingWireWire() arch API, streamline getConflictingXY semanticClifford Wolf2018-11-111-5/+10
| | * | Add getConflictingPipWire() arch API, router1 improvementsClifford Wolf2018-11-111-0/+5
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| * | Mark getArchOptions as override in derived classesPedro Vanzella2018-11-131-1/+1
* | | ecp5: Copy clock constraints during global promotionDavid Shah2018-11-121-0/+7
* | | timing: Add support for clock constraintsDavid Shah2018-11-121-0/+4
* | | ecp5: EBR clocking fixDavid Shah2018-11-121-5/+8
* | | ecp5: Update arch to new timing APIDavid Shah2018-11-122-15/+72
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* | ecp5: Fix 85k PLL_LRDavid Shah2018-11-111-1/+2
* | show 4th tresllis_io in tile boundsMiodrag Milanovic2018-11-111-1/+1
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* ecp5: Allow setting IO SLEWRATEDavid Shah2018-11-011-0/+2
* ecp5: Add PLL supportDavid Shah2018-10-314-7/+168
* ecp5: Separate global promotion and routingDavid Shah2018-10-314-33/+87
* ecp5: Add IO buffer insertionDavid Shah2018-10-314-15/+70
* ecp5: Adding LPF parserDavid Shah2018-10-313-0/+122
* ecp5: DSP fixesDavid Shah2018-10-222-33/+42
* ecp5: Working on DSPsDavid Shah2018-10-222-83/+200
* ecp5: Adding DSP supportDavid Shah2018-10-213-1/+799
* ecp5: Implement ECP5 equivalent of c9059fcDavid Shah2018-10-211-0/+9
* clangformatDavid Shah2018-10-162-5/+9
* ecp5: Add support for correct tile naming in all variantsDavid Shah2018-10-164-4/+84
* ecp5: Add DP16KD timing analysisDavid Shah2018-10-161-2/+29
* ecp5: Optimise DCC placementDavid Shah2018-10-141-3/+12
* ecp5: Fix BRAM tile namesDavid Shah2018-10-111-1/+1
* ecp5: Fixing BRAM initialisationDavid Shah2018-10-101-4/+14
* ecp5: Working on BRAM initialisationDavid Shah2018-10-093-0/+82
* ecp5: BRAM improvements with constant/inverted inputsDavid Shah2018-10-062-14/+80
* ecp5: Fixing EBR constant tie-offsDavid Shah2018-10-052-1/+51
* ecp5: Bitstream gen for DP16KD BRAMDavid Shah2018-10-051-0/+98
* ecp5: Infrastructure for BRAM bitstream genDavid Shah2018-10-053-0/+56
* ecp5: Dummy timing entry for BRAMDavid Shah2018-10-051-0/+3
* ecp5: Adding constids for blockramDavid Shah2018-10-051-0/+118
* ecp5: Negative clock support, general slice improvementsDavid Shah2018-10-023-4/+41
* ecp5: Small DRAM routing fixesDavid Shah2018-10-012-7/+25
* clangformatDavid Shah2018-10-013-6/+4
* ecp5: Fix packing of FFs into carry/DRAM slicesDavid Shah2018-10-011-4/+12
* ecp5: Fix DRAM initialisationDavid Shah2018-10-011-2/+2
* ecp5: Remove broken DRAM timing arcDavid Shah2018-10-011-2/+2
* ecp5: Debugging DRAM packingDavid Shah2018-10-013-6/+17
* ecp5: Working on DRAM packingDavid Shah2018-10-012-1/+68
* ecp5: Handling of DRAM initialisation and wiringDavid Shah2018-10-011-1/+59
* ecp5: Helper functions for distributed RAM supportDavid Shah2018-10-013-0/+64
* ecp5: Improve handling of constant CCU2C inputsDavid Shah2018-10-011-9/+65
* ecp5: Fix carry feed outDavid Shah2018-09-301-1/+1
* ecp5: Improve mixed no-FF/FF placementDavid Shah2018-09-304-30/+45
* ecp5: Carry packing fixesDavid Shah2018-09-301-13/+18
* ecp5: Relative placement and bitstream gen for carriesDavid Shah2018-09-303-2/+37
* ecp5: First stages of carry packingDavid Shah2018-09-301-3/+63
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