Commit message (Expand) | Author | Age | Files | Lines | ||
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* | | proper h06 and v06 | Miodrag Milanovic | 2019-11-11 | 1 | -34/+39 | |
* | | More pips added | Miodrag Milanovic | 2019-11-10 | 1 | -41/+200 | |
* | | more pips, and valid mapping | Miodrag Milanovic | 2019-11-10 | 2 | -10/+23 | |
* | | Fixed V2, some more pips | Miodrag Milanovic | 2019-11-10 | 1 | -12/+43 | |
* | | more pips | Miodrag Milanovic | 2019-11-10 | 1 | -2/+43 | |
* | | Draw some pips, fixed H6 and V6 | Miodrag Milanovic | 2019-11-09 | 3 | -31/+58 | |
* | | Show V02/V06/H02/H06 | Miodrag Milanovic | 2019-10-25 | 3 | -13/+105 | |
* | | display horizontal wires, add some globals to list | Miodrag Milanovic | 2019-10-23 | 4 | -1/+123 | |
* | | Split graphics calls for wires into gfx.cc | Miodrag Milanovic | 2019-10-20 | 3 | -268/+304 | |
* | | type needs to be part of hash for GroupId | Miodrag Milanovic | 2019-10-20 | 1 | -1/+3 | |
* | | muxes only together with slices | Miodrag Milanovic | 2019-10-20 | 1 | -9/+7 | |
* | | Remove not used line | Miodrag Milanovic | 2019-10-20 | 1 | -2/+0 | |
* | | Simplify layout of elements | Miodrag Milanovic | 2019-10-20 | 4 | -400/+254 | |
* | | fix slice wire | Miodrag Milanovic | 2019-10-20 | 1 | -20/+20 | |
* | | bound signals | Miodrag Milanovic | 2019-10-20 | 1 | -0/+65 | |
* | | more wires between switchboxes | Miodrag Milanovic | 2019-10-20 | 4 | -2/+59 | |
* | | Add more types of wires | Miodrag Milanovic | 2019-10-20 | 2 | -177/+221 | |
* | | Less types needed | Miodrag Milanovic | 2019-10-20 | 2 | -56/+24 | |
* | | finixed slice wires | Miodrag Milanovic | 2019-10-20 | 1 | -0/+27 | |
* | | wd wires | Miodrag Milanovic | 2019-10-20 | 2 | -1/+32 | |
* | | Fix look of some wires | Miodrag Milanovic | 2019-10-20 | 1 | -6/+9 | |
* | | Add output wires | Miodrag Milanovic | 2019-10-20 | 1 | -0/+35 | |
* | | fix mux display | Miodrag Milanovic | 2019-10-20 | 1 | -2/+2 | |
* | | set wire active flag | Miodrag Milanovic | 2019-10-20 | 2 | -1/+3 | |
* | | clk and lsr muxes | Miodrag Milanovic | 2019-10-20 | 2 | -1/+93 | |
* | | draw rest of slice wires and more from switchbox | Miodrag Milanovic | 2019-10-20 | 2 | -7/+106 | |
* | | Optimize | Miodrag Milanovic | 2019-10-20 | 2 | -18/+87 | |
* | | Add other side of slice wires | Miodrag Milanovic | 2019-10-20 | 2 | -14/+118 | |
* | | Display rest of slice input wires | Miodrag Milanovic | 2019-10-20 | 2 | -3/+69 | |
* | | Start adding visible wires | Miodrag Milanovic | 2019-10-20 | 5 | -10/+99 | |
* | | Added type to wire | Miodrag Milanovic | 2019-10-20 | 3 | -1/+87 | |
* | | Draw swbox, smaller slices, proper io | Miodrag Milanovic | 2019-10-20 | 4 | -28/+157 | |
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* | ecp5: Add support for ECLKBRIDGECS | David Shah | 2019-10-11 | 1 | -1/+52 | |
* | ecp5: Fix tristate IO registers | David Shah | 2019-10-09 | 1 | -3/+9 | |
* | ecp5: Add support for IO registers | David Shah | 2019-10-09 | 2 | -0/+103 | |
* | ecp5: Add IDDR71B support | David Shah | 2019-10-09 | 2 | -3/+16 | |
* | ecp5: Add ODDR71B support | David Shah | 2019-10-09 | 1 | -3/+14 | |
* | ecp5: Preparations for new IO bels | David Shah | 2019-10-09 | 3 | -1/+16 | |
* | ecp5: Fix parameters | David Shah | 2019-10-04 | 1 | -0/+4 | |
* | ecp5: Adding support for 36-bit wide PDP RAMs | David Shah | 2019-10-01 | 4 | -19/+96 | |
* | Merge pull request #332 from YosysHQ/dave/python-refactor | David Shah | 2019-09-19 | 1 | -96/+2 | |
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| * | python: Refactor out bindings shared between ECP5 and iCE40 | David Shah | 2019-09-15 | 1 | -96/+2 | |
* | | Merge branch 'precompiled-bba' of https://github.com/xobs/nextpnr into xobs-p... | David Shah | 2019-09-19 | 1 | -18/+31 | |
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| * | | ecp5: add support for PREGENERATED_BBA_PATH | Sean Cross | 2019-09-17 | 1 | -18/+31 | |
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* | | Merge pull request #330 from zeldin/bba | David Shah | 2019-09-19 | 1 | -5/+6 | |
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| * | CMake: Generate chipdbs in build tree when building out-of-tree | Marcus Comstedt | 2019-09-15 | 1 | -3/+4 | |
| * | bba: Require explicit endianness flag, and supply it | Marcus Comstedt | 2019-09-15 | 1 | -2/+2 | |
* | | python: Fix getWireBelPins | David Shah | 2019-09-15 | 2 | -0/+20 | |
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* | Merge pull request #329 from YosysHQ/dave/net_aliases | David Shah | 2019-09-13 | 1 | -0/+5 | |
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| * | json: Add support for net aliases | David Shah | 2019-09-13 | 1 | -0/+5 |