Commit message (Expand) | Author | Age | Files | Lines | ||
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... | ||||||
* | | more new wires added | Miodrag Milanovic | 2019-12-14 | 5 | -2/+214 | |
* | | ebr, mult and alu nice display | Miodrag Milanovic | 2019-12-14 | 2 | -8/+15 | |
* | | add more | Miodrag Milanovic | 2019-12-13 | 3 | -4/+44 | |
* | | new wires in db | Miodrag Milanovic | 2019-12-13 | 3 | -20/+498 | |
* | | added siologic | Miodrag Milanovic | 2019-12-13 | 4 | -2/+63 | |
* | | Add many new wires | Miodrag Milanovic | 2019-12-13 | 4 | -0/+1250 | |
* | | clangformat run | Miodrag Milanovic | 2019-12-08 | 3 | -329/+364 | |
* | | display IOs properly | Miodrag Milanovic | 2019-12-07 | 1 | -21/+5 | |
* | | More bels show properly | Miodrag Milanovic | 2019-12-07 | 1 | -43/+82 | |
* | | add dcca bels and dummy parts for other bels | Miodrag Milanovic | 2019-12-07 | 1 | -9/+54 | |
* | | Fix edge wires | Miodrag Milanovic | 2019-12-07 | 1 | -69/+108 | |
* | | add more pips | Miodrag Milanovic | 2019-12-01 | 1 | -0/+49 | |
* | | Handle H00 and V00 | Miodrag Milanovic | 2019-11-11 | 1 | -6/+49 | |
* | | More pips and fix for V01 | Miodrag Milanovic | 2019-11-11 | 1 | -42/+170 | |
* | | cleanup | Miodrag Milanovic | 2019-11-11 | 1 | -174/+78 | |
* | | proper h06 and v06 | Miodrag Milanovic | 2019-11-11 | 1 | -34/+39 | |
* | | More pips added | Miodrag Milanovic | 2019-11-10 | 1 | -41/+200 | |
* | | more pips, and valid mapping | Miodrag Milanovic | 2019-11-10 | 2 | -10/+23 | |
* | | Fixed V2, some more pips | Miodrag Milanovic | 2019-11-10 | 1 | -12/+43 | |
* | | more pips | Miodrag Milanovic | 2019-11-10 | 1 | -2/+43 | |
* | | Draw some pips, fixed H6 and V6 | Miodrag Milanovic | 2019-11-09 | 3 | -31/+58 | |
* | | Show V02/V06/H02/H06 | Miodrag Milanovic | 2019-10-25 | 3 | -13/+105 | |
* | | display horizontal wires, add some globals to list | Miodrag Milanovic | 2019-10-23 | 4 | -1/+123 | |
* | | Split graphics calls for wires into gfx.cc | Miodrag Milanovic | 2019-10-20 | 3 | -268/+304 | |
* | | type needs to be part of hash for GroupId | Miodrag Milanovic | 2019-10-20 | 1 | -1/+3 | |
* | | muxes only together with slices | Miodrag Milanovic | 2019-10-20 | 1 | -9/+7 | |
* | | Remove not used line | Miodrag Milanovic | 2019-10-20 | 1 | -2/+0 | |
* | | Simplify layout of elements | Miodrag Milanovic | 2019-10-20 | 4 | -400/+254 | |
* | | fix slice wire | Miodrag Milanovic | 2019-10-20 | 1 | -20/+20 | |
* | | bound signals | Miodrag Milanovic | 2019-10-20 | 1 | -0/+65 | |
* | | more wires between switchboxes | Miodrag Milanovic | 2019-10-20 | 4 | -2/+59 | |
* | | Add more types of wires | Miodrag Milanovic | 2019-10-20 | 2 | -177/+221 | |
* | | Less types needed | Miodrag Milanovic | 2019-10-20 | 2 | -56/+24 | |
* | | finixed slice wires | Miodrag Milanovic | 2019-10-20 | 1 | -0/+27 | |
* | | wd wires | Miodrag Milanovic | 2019-10-20 | 2 | -1/+32 | |
* | | Fix look of some wires | Miodrag Milanovic | 2019-10-20 | 1 | -6/+9 | |
* | | Add output wires | Miodrag Milanovic | 2019-10-20 | 1 | -0/+35 | |
* | | fix mux display | Miodrag Milanovic | 2019-10-20 | 1 | -2/+2 | |
* | | set wire active flag | Miodrag Milanovic | 2019-10-20 | 2 | -1/+3 | |
* | | clk and lsr muxes | Miodrag Milanovic | 2019-10-20 | 2 | -1/+93 | |
* | | draw rest of slice wires and more from switchbox | Miodrag Milanovic | 2019-10-20 | 2 | -7/+106 | |
* | | Optimize | Miodrag Milanovic | 2019-10-20 | 2 | -18/+87 | |
* | | Add other side of slice wires | Miodrag Milanovic | 2019-10-20 | 2 | -14/+118 | |
* | | Display rest of slice input wires | Miodrag Milanovic | 2019-10-20 | 2 | -3/+69 | |
* | | Start adding visible wires | Miodrag Milanovic | 2019-10-20 | 5 | -10/+99 | |
* | | Added type to wire | Miodrag Milanovic | 2019-10-20 | 3 | -1/+87 | |
* | | Draw swbox, smaller slices, proper io | Miodrag Milanovic | 2019-10-20 | 4 | -28/+157 | |
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* | ecp5: Add support for ECLKBRIDGECS | David Shah | 2019-10-11 | 1 | -1/+52 | |
* | ecp5: Fix tristate IO registers | David Shah | 2019-10-09 | 1 | -3/+9 | |
* | ecp5: Add support for IO registers | David Shah | 2019-10-09 | 2 | -0/+103 |