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* Use NEXTPNR_NAMESPACE macro's now that headers are seperated.Keith Rothman2021-03-151-1/+1
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* clangformatgatecat2021-03-031-1/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Initial LUT rotation logic.Keith Rothman2021-02-261-1/+196
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Fix assorted bugs in FPGA interchange.Keith Rothman2021-02-231-85/+158
| | | | | | | | | | Fixes: - Only use map constant pins during routing, and not during placement. - Unmapped cell ports have no BEL pins. - Fix SiteRouter congestion not taking into account initial expansion. - Fix psuedo-site pip output. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Finish dedicated interconnect implementation.Keith Rothman2021-02-231-9/+36
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Working FF example now that constant merging is done.Keith Rothman2021-02-231-5/+182
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add initial logic for handling dedicated interconnect situations.Keith Rothman2021-02-231-0/+5
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Remove some signedness warnings.Keith Rothman2021-02-231-1/+1
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add initial constant network support to FPGA interchange arch.Keith Rothman2021-02-231-1/+1
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-191-1/+1
| | | | | | | | | | | | | | | | | This replaces the arch-specific DelayInfo structure with new DelayPair (min/max only) and DelayQuad (min/max for both rise and fall) structures that form part of common code. This further reduces the amount of arch-specific code; and also provides useful data structures for timing analysis which will need to delay with pairs/quads of delays as it is improved. While there may be a small performance cost to arches that didn't separate the rise/fall cases (arches that aren't currently separating the min/max cases just need to be fixed...) in DelayInfo, my expectation is that inlining will mean this doesn't make much difference. Signed-off-by: gatecat <gatecat@ds0.me>
* Add some utility methods for site instance access.Keith Rothman2021-02-181-2/+2
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Refactor "get only from iterator" to a utility.Keith Rothman2021-02-171-5/+2
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Change how package pin IO sites are selected.Keith Rothman2021-02-171-1/+17
| | | | | | | The first site type that matches is now selected, under the premise that the early site types are more general. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Continue fixes.Keith Rothman2021-02-171-0/+12
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add initial site router.Keith Rothman2021-02-171-1/+1
| | | | | | | | This site router likely cannot handle the full problem space. It may need to be replaced with a more generalize approach as testing continues. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Working on standing up initial constraints system.Keith Rothman2021-02-171-11/+76
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* clangformatgatecat2021-02-171-3/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Require `--package` when arch BBA contains multiple packages.Keith Rothman2021-02-161-3/+11
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* [FPGA Interchange] Add Cell -> BEL Pin maps.Keith Rothman2021-02-161-7/+161
| | | | | | | This also expands the FPGA interchange Arch BBA to include placement constraints, but doesn't implement them yet. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add FPGA interchange frontend and backend.Keith Rothman2021-02-151-2/+19
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Run "make clangformat".Keith Rothman2021-02-121-5/+5
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Refactor XDC parser into a little class for testing purposes.Keith Rothman2021-02-121-0/+11
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add FPGA interchange XDC parser.Keith Rothman2021-02-121-0/+7
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* interchange: Base on ArchAPID. Shah2021-02-081-3/+1
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* Add RelSlice::ssize and use it when comparing with signed ints.Keith Rothman2021-02-051-14/+14
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Move all string data into BBA file.Keith Rothman2021-02-051-8/+8
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Use RelSlice instead of RelPtr in cases where sizes are present.Keith Rothman2021-02-041-17/+17
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Update APIs to conform to style guide.Keith Rothman2021-02-041-10/+10
| | | | | | | - Change non-Arch methods to snake_case - Adds some utility functions to for accessing bel_data. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Update copywrite headers.Keith Rothman2021-02-041-1/+2
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Fix warnings with signed/unsigned.Keith Rothman2021-02-041-1/+1
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Run "make clangformat".Keith Rothman2021-02-041-36/+23
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Update FPGA interchange to use IdStringList.Keith Rothman2021-02-041-100/+112
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Start adding data for placement constraint solving.Keith Rothman2021-02-041-45/+21
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add initial updates to FPGA interchange arch for BEL buckets.Keith Rothman2021-02-041-0/+7
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Address review comments.Keith Rothman2021-02-041-8/+5
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Fix BBA import bugs.Keith Rothman2021-02-041-48/+155
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Assorted fixes to new FPGA interchange based arch.Keith Rothman2021-02-041-4/+12
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Initial compiling version.Keith Rothman2021-02-041-0/+9
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Initial FPGA interchange (which is just a cut-down xilinx arch).Keith Rothman2021-02-041-0/+474
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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