index
:
iCE40/nextpnr
master
[no description]
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
fpga_interchange
/
arch.cc
Commit message (
Expand
)
Author
Age
Files
Lines
*
interchange: Allow pseudo pip wires to overlap with bound site wires on the s...
gatecat
2021-07-06
1
-8
/
+3
*
Merge pull request #744 from YosysHQ/gatecat/const-in-macro
gatecat
2021-07-01
1
-1
/
+1
|
\
|
*
interchange: Fix handling of constants in macros
gatecat
2021-07-01
1
-1
/
+1
*
|
interchange: Reserve site ports only reachable from dedicated routing
gatecat
2021-07-01
1
-0
/
+4
|
/
*
interchange: arch: move macro expansion step before ios packing
Alessandro Comodi
2021-06-18
1
-1
/
+1
*
Fixing old emails and names in copyrights
gatecat
2021-06-12
1
-2
/
+2
*
interchange: add support for generating BEL clusters
Alessandro Comodi
2021-06-11
1
-0
/
+1
*
Using hashlib in arches
gatecat
2021-06-02
1
-16
/
+3
*
Use hashlib for core netlist structures
gatecat
2021-06-02
1
-2
/
+2
*
interchange: Preliminary implementation of macro expansion
gatecat
2021-05-21
1
-0
/
+1
*
Run clangformat
gatecat
2021-05-16
1
-2
/
+1
*
interchange: site router: add valid pips list to check during routing
Alessandro Comodi
2021-05-13
1
-11
/
+15
*
interchange: arch: do not allow site pips within sites
Alessandro Comodi
2021-05-12
1
-6
/
+0
*
interchange: Fix bounding box computation
gatecat
2021-05-11
1
-2
/
+2
*
interchange: Adding a basic global buffer placer
gatecat
2021-05-07
1
-0
/
+10
*
interchange: Initial global routing implementation
gatecat
2021-05-07
1
-0
/
+20
*
interchange: Implement getWireType
gatecat
2021-04-30
1
-1
/
+18
*
interchange: Handle disconnected/missing cell pins
gatecat
2021-04-19
1
-0
/
+53
*
clangformat
gatecat
2021-04-12
1
-9
/
+10
*
interchange: Disambiguate cell and bel pins when creating Vcc ties
gatecat
2021-04-09
1
-6
/
+10
*
[interchange] Provide estimateDelay when USE_LOOKAHEAD is not defined.
Keith Rothman
2021-04-06
1
-1
/
+16
*
[interchange] Remove requirement to have wire_lut.
Keith Rothman
2021-04-06
1
-6
/
+0
*
[interchange] Scale edge cost of pseudo pips.
Keith Rothman
2021-04-06
1
-0
/
+11
*
[interchange] Disallow site edges during general routing.
Keith Rothman
2021-04-06
1
-5
/
+22
*
[interchange] Add crude pseudo pip model.
Keith Rothman
2021-04-06
1
-4
/
+35
*
[interchange] Update to v6 of FPGA interchange chipdb.
Keith Rothman
2021-04-01
1
-1
/
+6
*
[interchange] Fix site pip check for drivers.
Keith Rothman
2021-03-30
1
-7
/
+22
*
Implement debugging tools for site router.
Keith Rothman
2021-03-25
1
-0
/
+30
*
Re-work LUT mapping logic to only put VCC pins when required.
Keith Rothman
2021-03-25
1
-98
/
+35
*
Fixup some of the re-mapping logic.
Keith Rothman
2021-03-25
1
-24
/
+74
*
Add initial handling of local site inverters and constant signals.
Keith Rothman
2021-03-25
1
-20
/
+95
*
Merge pull request #643 from litghost/id_constants
gatecat
2021-03-23
1
-4
/
+25
|
\
|
*
[FPGA interchange] Convert some string constants to IdString.
Keith Rothman
2021-03-23
1
-4
/
+25
*
|
Initial version of inverter logic.
Keith Rothman
2021-03-23
1
-0
/
+31
*
|
Use new parameter definition data in FPGA interchange processing.
Keith Rothman
2021-03-23
1
-41
/
+5
|
/
*
Initial lookahead for FPGA interchange.
Keith Rothman
2021-03-23
1
-13
/
+39
*
Merge pull request #637 from litghost/refine_site_router
gatecat
2021-03-22
1
-2
/
+30
|
\
|
*
Rework FPGA interchange site router.
Keith Rothman
2021-03-22
1
-2
/
+30
*
|
Add "checkPipAvailForNet" to Arch API.
Keith Rothman
2021-03-22
1
-2
/
+2
|
/
*
Add pseudo pip data to chipdb (with schema bump).
Keith Rothman
2021-03-22
1
-5
/
+127
*
Refactor header structures in FPGA interchange Arch.
Keith Rothman
2021-03-19
1
-9
/
+285
*
Use NEXTPNR_NAMESPACE macro's now that headers are seperated.
Keith Rothman
2021-03-15
1
-1
/
+1
*
clangformat
gatecat
2021-03-03
1
-1
/
+2
*
Initial LUT rotation logic.
Keith Rothman
2021-02-26
1
-1
/
+196
*
Fix assorted bugs in FPGA interchange.
Keith Rothman
2021-02-23
1
-85
/
+158
*
Finish dedicated interconnect implementation.
Keith Rothman
2021-02-23
1
-9
/
+36
*
Working FF example now that constant merging is done.
Keith Rothman
2021-02-23
1
-5
/
+182
*
Add initial logic for handling dedicated interconnect situations.
Keith Rothman
2021-02-23
1
-0
/
+5
*
Remove some signedness warnings.
Keith Rothman
2021-02-23
1
-1
/
+1
*
Add initial constant network support to FPGA interchange arch.
Keith Rothman
2021-02-23
1
-1
/
+1
[next]