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fpga_interchange
/
arch.h
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Author
Age
Files
Lines
*
Use NEXTPNR_NAMESPACE macro's now that headers are seperated.
Keith Rothman
2021-03-15
1
-1
/
+1
*
Split nextpnr.h to allow for linear inclusion.
Keith Rothman
2021-03-15
1
-7
/
+9
*
Initial LUT rotation logic.
Keith Rothman
2021-02-26
1
-1
/
+34
*
Fix assorted bugs in FPGA interchange.
Keith Rothman
2021-02-23
1
-33
/
+21
*
Working FF example now that constant merging is done.
Keith Rothman
2021-02-23
1
-1
/
+3
*
Add initial logic for handling dedicated interconnect situations.
Keith Rothman
2021-02-23
1
-5
/
+9
*
Fix reference copy.
Keith Rothman
2021-02-23
1
-6
/
+6
*
Run "make clangformat".
Keith Rothman
2021-02-23
1
-6
/
+8
*
Initial working constant network support!
Keith Rothman
2021-02-23
1
-4
/
+32
*
Add initial constant network support to FPGA interchange arch.
Keith Rothman
2021-02-23
1
-6
/
+46
*
Change CellInfo in getBelPinsForCellPin to be const.
Keith Rothman
2021-02-23
1
-1
/
+1
*
Replace DelayInfo with DelayPair/DelayQuad
gatecat
2021-02-19
1
-14
/
+4
*
Fix sign mismatch.
Keith Rothman
2021-02-18
1
-1
/
+1
*
Add some utility methods for site instance access.
Keith Rothman
2021-02-18
1
-5
/
+37
*
Refactor "get only from iterator" to a utility.
Keith Rothman
2021-02-17
1
-1
/
+5
*
Continue fixes.
Keith Rothman
2021-02-17
1
-10
/
+3
*
Add initial site router.
Keith Rothman
2021-02-17
1
-4
/
+58
*
Working on standing up initial constraints system.
Keith Rothman
2021-02-17
1
-14
/
+177
*
Merge pull request #586 from litghost/add_cell_bel_mapping_only
gatecat
2021-02-17
1
-6
/
+105
|
\
|
*
[FPGA Interchange] Add Cell -> BEL Pin maps.
Keith Rothman
2021-02-16
1
-6
/
+105
*
|
Remove isValidBelForCell
gatecat
2021-02-16
1
-11
/
+0
|
/
*
Add FPGA interchange frontend and backend.
Keith Rothman
2021-02-15
1
-0
/
+10
*
Merge pull request #575 from YosysHQ/gatecat/belpin-2
gatecat
2021-02-15
1
-0
/
+3
|
\
|
*
Add getBelPinsForCellPin to Arch API
gatecat
2021-02-10
1
-0
/
+3
*
|
Add FPGA interchange XDC parser.
Keith Rothman
2021-02-12
1
-1
/
+4
*
|
Add getBelHidden and add some missing "override" statements.
Keith Rothman
2021-02-11
1
-2
/
+1
|
/
*
interchange: Base on ArchAPI
D. Shah
2021-02-08
1
-103
/
+134
*
Add RelSlice::ssize and use it when comparing with signed ints.
Keith Rothman
2021-02-05
1
-13
/
+14
*
Move all string data into BBA file.
Keith Rothman
2021-02-05
1
-6
/
+7
*
Use RelSlice instead of RelPtr in cases where sizes are present.
Keith Rothman
2021-02-04
1
-80
/
+50
*
Update APIs to conform to style guide.
Keith Rothman
2021-02-04
1
-52
/
+55
*
Remove unused method getReservedWireNet.
Keith Rothman
2021-02-04
1
-7
/
+0
*
Update copywrite headers.
Keith Rothman
2021-02-04
1
-1
/
+2
*
Run "make clangformat".
Keith Rothman
2021-02-04
1
-104
/
+73
*
Update FPGA interchange to use IdStringList.
Keith Rothman
2021-02-04
1
-32
/
+25
*
Start adding data for placement constraint solving.
Keith Rothman
2021-02-04
1
-5
/
+22
*
Debug BEL bucket data.
Keith Rothman
2021-02-04
1
-11
/
+14
*
Add initial updates to FPGA interchange arch for BEL buckets.
Keith Rothman
2021-02-04
1
-0
/
+204
*
Address review comments.
Keith Rothman
2021-02-04
1
-0
/
+1
*
Fix BBA import bugs.
Keith Rothman
2021-02-04
1
-21
/
+46
*
Assorted fixes to new FPGA interchange based arch.
Keith Rothman
2021-02-04
1
-1
/
+1
*
Initial compiling version.
Keith Rothman
2021-02-04
1
-16
/
+16
*
Initial FPGA interchange (which is just a cut-down xilinx arch).
Keith Rothman
2021-02-04
1
-0
/
+1096