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path: root/fpga_interchange/arch_pybindings.cc
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* Fixing old emails and names in copyrightsgatecat2021-06-121-1/+1
* Use hashlib for core netlist structuresgatecat2021-06-021-4/+4
* Add Python bindings for placement testsgatecat2021-04-151-0/+5
* Remove isValidBelForCellgatecat2021-02-161-3/+0
* Update copywrite headers.Keith Rothman2021-02-041-0/+1
* Add initial updates to FPGA interchange arch for BEL buckets.Keith Rothman2021-02-041-0/+2
* Initial FPGA interchange (which is just a cut-down xilinx arch).Keith Rothman2021-02-041-0/+74