| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Fix small isses and code formatting | Maciej Dudek | 2021-09-27 | 1 | -11/+7 |
| | | | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com> | ||||
| * | Change Cluster placement algorithm | Maciej Dudek | 2021-09-23 | 1 | -0/+9 |
| | | | | | | | | Use physical placement from device DB It should reduce runtime Signed-off-by: Maciej Dudek <mdudek@antmicro.com> | ||||
| * | Adding MacroCell placement | Maciej Dudek | 2021-09-23 | 1 | -2/+2 |
| | | | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com> | ||||
| * | Adding support for MacroCells | Maciej Dudek | 2021-09-23 | 1 | -1/+40 |
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| * | interchange: disallow placing cells on sites with clusters | Alessandro Comodi | 2021-08-27 | 1 | -1/+2 |
| | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
| * | [interchange] Update chipdb and python-fpga-interchange versions | Maciej Dudek | 2021-07-14 | 1 | -1/+1 |
| | | | | | Signed-off-by: Maciej Dudek <mdudek@antmicro.com> | ||||
| * | interchange: update chipdb version | Alessandro Comodi | 2021-07-08 | 1 | -1/+1 |
| | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
| * | interchange: reduce run-time to check dedicated interconnect | Alessandro Comodi | 2021-07-08 | 1 | -0/+1 |
| | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
| * | interchange: increase chipinfo version | Alessandro Comodi | 2021-06-11 | 1 | -1/+1 |
| | | | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
| * | interchange: add support for generating BEL clusters | Alessandro Comodi | 2021-06-11 | 1 | -0/+28 |
| | | | | | | | | | Clustering greatly helps the placer to identify and pack together specific cells at the same site (e.g. LUT+FF), or cells that are chained through dedicated interconnections (e.g. CARRY CHAINS) Signed-off-by: Alessandro Comodi <acomodi@antmicro.com> | ||||
| * | interchange: Add macro param map rules to chipdb | gatecat | 2021-05-21 | 1 | -0/+24 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | interchange: Add macro data to chipdb | gatecat | 2021-05-21 | 1 | -1/+51 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | interchange: Add more global cell info | gatecat | 2021-05-07 | 1 | -1/+14 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | interchange: Add wire types to chipdb | gatecat | 2021-04-30 | 1 | -1/+17 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | interchange: Add default cell connections to chipdb | gatecat | 2021-04-19 | 1 | -1/+24 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | [interchange] Update to v6 of FPGA interchange chipdb. | Keith Rothman | 2021-04-01 | 1 | -1/+2 |
| | | | | | | | | Changes: - Adds LUT output pin to LutBelPOD. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | ||||
| * | [FPGA interchange] Add support for global buffers from chipdb. | Keith Rothman | 2021-03-23 | 1 | -2/+7 |
| | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | ||||
| * | Update FPGA interchange chipdb to v4 with inverter data. | Keith Rothman | 2021-03-23 | 1 | -1/+22 |
| | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | ||||
| * | Update latest version of FPGA interchange schema. | Keith Rothman | 2021-03-23 | 1 | -1/+10 |
| | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | ||||
| * | Add pseudo pip data to chipdb (with schema bump). | Keith Rothman | 2021-03-22 | 1 | -1/+2 |
| | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | ||||
| * | Refactor header structures in FPGA interchange Arch. | Keith Rothman | 2021-03-19 | 1 | -0/+310 |
| Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | |||||
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