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* Fix bug where DedicateInterconnect incorrectly allows some placement.Keith Rothman2021-03-301-9/+22
| | | | | | | This occurs when the driver pin and sink pin are part of the same site, but not reachable with site routing only. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Implement debugging tools for site router.Keith Rothman2021-03-251-0/+29
| | | | | | | | - Finishes implementation of SiteArch::nameOfPip and SiteArch::nameOfWire - Adds "explain_bel_status", which should be an exhaustive diagnostic of the status of a BEL placement. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Fix compiler warnings introduced by -Wextragatecat2021-02-251-2/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Fix assorted bugs in FPGA interchange.Keith Rothman2021-02-231-264/+260
| | | | | | | | | | Fixes: - Only use map constant pins during routing, and not during placement. - Unmapped cell ports have no BEL pins. - Fix SiteRouter congestion not taking into account initial expansion. - Fix psuedo-site pip output. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Finish dedicated interconnect implementation.Keith Rothman2021-02-231-128/+566
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add initial logic for handling dedicated interconnect situations.Keith Rothman2021-02-231-0/+351
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>