| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Added fallback to VCC as the preferred constant if the architecture does not ↵ | Maciej Kurc | 2022-05-12 | 1 | -4/+2 |
| | | | | | | | specify one. Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| * | Added tying unused LUT pins to preferred constant instead of Vcc | Maciej Kurc | 2022-05-11 | 1 | -2/+8 |
| | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| * | Generalized representation of unused LUT pins connections | Maciej Kurc | 2022-05-11 | 1 | -38/+44 |
| | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| * | Added more code comments, formatted the code | Maciej Kurc | 2021-07-22 | 1 | -2/+3 |
| | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| * | LUT mapping ceche optimizations 2 | Maciej Kurc | 2021-07-16 | 1 | -80/+0 |
| | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| * | Working site LUT mapping cache | Maciej Kurc | 2021-07-16 | 1 | -15/+92 |
| | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| * | Using hashlib in arches | gatecat | 2021-06-02 | 1 | -7/+7 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | clangformat | gatecat | 2021-04-12 | 1 | -7/+4 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | [interchange] Prevent site router from generating incorrect LUTs. | Keith Rothman | 2021-04-06 | 1 | -6/+12 |
| | | | | | | | | | | The previous logic tied LUT input pins to VCC if a wire was unplacable. This missed a case where the net was present to the input of the LUT, but a wire was still not legal. This case is now prevented by tying the output of the LUT to an unused net. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | ||||
| * | [interchange] Add crude pseudo pip model. | Keith Rothman | 2021-04-06 | 1 | -1/+41 |
| | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | ||||
| * | Add some FIXME's around VCC assumption in LUT logic. | Keith Rothman | 2021-03-25 | 1 | -0/+17 |
| | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | ||||
| * | Re-work LUT mapping logic to only put VCC pins when required. | Keith Rothman | 2021-03-25 | 1 | -5/+111 |
| | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | ||||
| * | Refactor header structures in FPGA interchange Arch. | Keith Rothman | 2021-03-19 | 1 | -1/+17 |
| | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | ||||
| * | Use NEXTPNR_NAMESPACE macro's now that headers are seperated. | Keith Rothman | 2021-03-15 | 1 | -1/+1 |
| | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | ||||
| * | clangformat | gatecat | 2021-03-03 | 1 | -92/+86 |
| | | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
| * | Initial LUT rotation logic. | Keith Rothman | 2021-02-26 | 1 | -0/+370 |
| Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | |||||
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