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* Merge pull request #644 from litghost/add_global_buffersgatecat2021-03-234-10/+29
|\ | | | | [FPGA interchange] Add support for global buffers from chipdb.
| * [FPGA interchange] Add support for global buffers from chipdb.Keith Rothman2021-03-234-10/+29
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #643 from litghost/id_constantsgatecat2021-03-232-4/+27
|\ \ | | | | | | [FPGA interchange] Convert some string constants to IdString.
| * | [FPGA interchange] Convert some string constants to IdString.Keith Rothman2021-03-232-4/+27
| | | | | | | | | | | | | | | | | | Also add some optional diagnostic prints for cell -> BEL pin mapping. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | | Merge pull request #640 from litghost/inversion_logicgatecat2021-03-237-8/+131
|\ \ \ | | |/ | |/| Initial inverter logic for FPGA interchange
| * | Initial version of inverter logic.Keith Rothman2021-03-237-8/+131
| | | | | | | | | | | | | | | | | | | | | For now just implements some inspection capabilities, and the site router (for now) avoids inverted paths. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | | Merge pull request #639 from litghost/parameter_iterationgatecat2021-03-235-42/+315
|\| | | |/ |/| Update parameter processing based on new DeviceResources metadata
| * Update FPGA interchange chipdb to v4 with inverter data.Keith Rothman2021-03-231-1/+22
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Use new parameter definition data in FPGA interchange processing.Keith Rothman2021-03-234-41/+284
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * Update latest version of FPGA interchange schema.Keith Rothman2021-03-231-1/+10
| | | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #642 from YosysHQ/gatecat/missing-cell-pingatecat2021-03-231-0/+3
|\ \ | |/ |/| interchange: Add nice error for missing cell pins
| * interchange: Add nice error for missing cell pinsgatecat2021-03-231-0/+3
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Initial lookahead for FPGA interchange.Keith Rothman2021-03-2313-13/+2682
|/ | | | | | | | | Currently the lookahead is disabled by default because of the time to compute and RAM usage. However it does appear to work reasonably well in testing. Further effort is required to lower RAM usage after initial computation, and explore trade-off for cheaper time to compute. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Merge pull request #638 from litghost/fixup_physical_netlist_writergatecat2021-03-221-11/+93
|\ | | | | Correct some bugs in writing of physical netlist w.r.t. site sources.
| * Correct some bugs in writing of physical netlist w.r.t. site sources.Keith Rothman2021-03-221-11/+93
| | | | | | | | | | | | | | Local site sources should have their driving BEL pin included in the net so that the site wire is driven by an output BEL pin. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #637 from litghost/refine_site_routergatecat2021-03-2217-588/+2745
|\ \ | | | | | | Refine site router
| * | Rework FPGA interchange site router.Keith Rothman2021-03-2212-571/+2617
| | | | | | | | | | | | | | | | | | | | | The new site router should be robust to most situations, and isn't significantly slower with the use of caching. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * | Add missing dependencies to CMake targets.Keith Rothman2021-03-225-17/+128
| |/ | | | | | | | | | | | | - Add additional targets useful for various situations. - Have counter test use common remap.v file. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* | Merge pull request #634 from litghost/add_get_bel_pin_typegatecat2021-03-221-0/+4
|\ \ | | | | | | Add getBelPinType to Python interface.
| * | Add getBelPinType to Python interface.Keith Rothman2021-03-221-0/+4
| |/ | | | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* / Add "checkPipAvailForNet" to Arch API.Keith Rothman2021-03-222-3/+3
|/ | | | | | | | This is important for distiguishing valid pseudo pips in the FPGA interchange arch. This also avoids a double or triple lookup of pip->net map. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add pseudo pip data to chipdb (with schema bump).Keith Rothman2021-03-223-6/+143
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Refactor header structures in FPGA interchange Arch.Keith Rothman2021-03-198-891/+1289
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Fixup GUI link dependencies on headers from libraries.Keith Rothman2021-03-181-0/+5
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* fpga_interchange: temporarily disable failing testAlessandro Comodi2021-03-171-1/+2
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* fpga_interchange: minor fixes and comments additionAlessandro Comodi2021-03-163-22/+57
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* fpga_interchange: address review commentsAlessandro Comodi2021-03-169-18/+92
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* github-actions: use capnp v0.8.0Alessandro Comodi2021-03-161-1/+1
| | | | | | This also updates the note in the README for the FPGA interchange Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* fpga_interchange: re-add README with updated instructionsAlessandro Comodi2021-03-161-0/+69
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* fpga_interchange: tests: add techmap optional source fileAlessandro Comodi2021-03-164-3/+19
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* fpga_interchange: add bbasm step and archcheckAlessandro Comodi2021-03-167-41/+78
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* fpga_interchange: address review commentsAlessandro Comodi2021-03-164-32/+91
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* fpga_interchange: tests: added comment and fixed XDCAlessandro Comodi2021-03-1616-29/+74
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* fpga_interchange: chipdb: use generic patching functionAlessandro Comodi2021-03-163-41/+96
| | | | | | Also moved the RapidWright invocation script path under a CMake variable Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* fpga_interchange: cmake: generate only one device familyAlessandro Comodi2021-03-169-49/+72
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* fpga_interchange: tests: add cmake functionsAlessandro Comodi2021-03-1627-50/+215
| | | | | | Also move all tests in a tests directory Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* fpga_intrchange: add cmake infrastructure to generate chipdbsAlessandro Comodi2021-03-166-133/+122
| | | | Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
* Use NEXTPNR_NAMESPACE macro's now that headers are seperated.Keith Rothman2021-03-154-5/+5
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Split nextpnr.h to allow for linear inclusion.Keith Rothman2021-03-155-25/+42
| | | | | | | | | | | | | | | | | | | "nextpnr.h" is no longer the god header. Important improvements: - Functions in log.h can be used without including BaseCtx/Arch/Context. This means that log_X functions can be called without included "nextpnr.h" - NPNR_ASSERT can be used without including "nextpnr.h" by including "nextpnr_assertions.h". This allows NPNR_ASSERT to be used safely in any header file. - Types defined in "archdefs.h" are now available without including BaseCtx/Arch/Context. This means that utility classes that will be used inside of BaseCtx/Arch/Context can be defined safely in a self-contained header. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* clangformatgatecat2021-03-033-114/+108
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Update FPGA interchange README.Keith Rothman2021-02-261-11/+7
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* For now just return false in the site router.Keith Rothman2021-02-261-1/+1
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Initial LUT rotation logic.Keith Rothman2021-02-267-7/+739
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add counter test.Keith Rothman2021-02-265-0/+71
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Fix compiler warnings introduced by -Wextragatecat2021-02-252-3/+3
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Fix assorted bugs in FPGA interchange.Keith Rothman2021-02-238-422/+626
| | | | | | | | | | Fixes: - Only use map constant pins during routing, and not during placement. - Unmapped cell ports have no BEL pins. - Fix SiteRouter congestion not taking into account initial expansion. - Fix psuedo-site pip output. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Finish dedicated interconnect implementation.Keith Rothman2021-02-233-139/+611
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Working FF example now that constant merging is done.Keith Rothman2021-02-236-8/+218
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add initial logic for handling dedicated interconnect situations.Keith Rothman2021-02-2311-26/+587
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Move RapidWright git URI back to upstream.Keith Rothman2021-02-231-5/+1
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-07 13:06:31 +0000