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authorgatecat <gatecat@ds0.me>2021-03-22 18:31:48 +0000
committerGitHub <noreply@github.com>2021-03-22 18:31:48 +0000
commite8d36bf5bdda84503d5c796b933b1c986a277bf5 (patch)
tree18934e6784c4bb0b4a083389e86c78f45c8a2cb1 /fpga_interchange
parentf6ae068cb205527d63d93e5b3581b85a22f90f34 (diff)
parent4cd74bba2c010e4d714ec72fe11128069ea0495a (diff)
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Merge pull request #634 from litghost/add_get_bel_pin_type
Add getBelPinType to Python interface.
Diffstat (limited to 'fpga_interchange')
-rw-r--r--fpga_interchange/examples/devices/xc7a35t/test_data.yaml4
1 files changed, 4 insertions, 0 deletions
diff --git a/fpga_interchange/examples/devices/xc7a35t/test_data.yaml b/fpga_interchange/examples/devices/xc7a35t/test_data.yaml
index 268d180a..88c6feda 100644
--- a/fpga_interchange/examples/devices/xc7a35t/test_data.yaml
+++ b/fpga_interchange/examples/devices/xc7a35t/test_data.yaml
@@ -34,3 +34,7 @@ bel_pin_test:
- bel: $CONSTANTS_X0Y0.$CONSTANTS/VCC
pin: P
wire: $CONSTANTS_X0Y0.$CONSTANTS/$VCC_SOURCE
+ - bel: SLICE_X1Y19.SLICEL/SRUSEDGND
+ pin: "0"
+ wire: SLICE_X1Y19.SLICEL/SRUSEDGND_HARD0
+ type: PORT_OUT