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* Add "checkPipAvailForNet" to Arch API.Keith Rothman2021-03-222-3/+3
* Add pseudo pip data to chipdb (with schema bump).Keith Rothman2021-03-223-6/+143
* Refactor header structures in FPGA interchange Arch.Keith Rothman2021-03-198-891/+1289
* Fixup GUI link dependencies on headers from libraries.Keith Rothman2021-03-181-0/+5
* fpga_interchange: temporarily disable failing testAlessandro Comodi2021-03-171-1/+2
* fpga_interchange: minor fixes and comments additionAlessandro Comodi2021-03-163-22/+57
* fpga_interchange: address review commentsAlessandro Comodi2021-03-169-18/+92
* github-actions: use capnp v0.8.0Alessandro Comodi2021-03-161-1/+1
* fpga_interchange: re-add README with updated instructionsAlessandro Comodi2021-03-161-0/+69
* fpga_interchange: tests: add techmap optional source fileAlessandro Comodi2021-03-164-3/+19
* fpga_interchange: add bbasm step and archcheckAlessandro Comodi2021-03-167-41/+78
* fpga_interchange: address review commentsAlessandro Comodi2021-03-164-32/+91
* fpga_interchange: tests: added comment and fixed XDCAlessandro Comodi2021-03-1616-29/+74
* fpga_interchange: chipdb: use generic patching functionAlessandro Comodi2021-03-163-41/+96
* fpga_interchange: cmake: generate only one device familyAlessandro Comodi2021-03-169-49/+72
* fpga_interchange: tests: add cmake functionsAlessandro Comodi2021-03-1627-50/+215
* fpga_intrchange: add cmake infrastructure to generate chipdbsAlessandro Comodi2021-03-166-133/+122
* Use NEXTPNR_NAMESPACE macro's now that headers are seperated.Keith Rothman2021-03-154-5/+5
* Split nextpnr.h to allow for linear inclusion.Keith Rothman2021-03-155-25/+42
* clangformatgatecat2021-03-033-114/+108
* Update FPGA interchange README.Keith Rothman2021-02-261-11/+7
* For now just return false in the site router.Keith Rothman2021-02-261-1/+1
* Initial LUT rotation logic.Keith Rothman2021-02-267-7/+739
* Add counter test.Keith Rothman2021-02-265-0/+71
* Fix compiler warnings introduced by -Wextragatecat2021-02-252-3/+3
* Fix assorted bugs in FPGA interchange.Keith Rothman2021-02-238-422/+626
* Finish dedicated interconnect implementation.Keith Rothman2021-02-233-139/+611
* Working FF example now that constant merging is done.Keith Rothman2021-02-236-8/+218
* Add initial logic for handling dedicated interconnect situations.Keith Rothman2021-02-2311-26/+587
* Move RapidWright git URI back to upstream.Keith Rothman2021-02-231-5/+1
* Remove some signedness warnings.Keith Rothman2021-02-231-1/+1
* Fix reference copy.Keith Rothman2021-02-231-6/+6
* Run "make clangformat".Keith Rothman2021-02-231-6/+8
* Initial working constant network support!Keith Rothman2021-02-234-14/+145
* Add constant network test case.Keith Rothman2021-02-235-0/+42
* Add tests to confirm constant routing import.Keith Rothman2021-02-232-0/+36
* Correct some bugs in the create_bba Makefile.Keith Rothman2021-02-231-3/+9
* Add initial constant network support to FPGA interchange arch.Keith Rothman2021-02-232-7/+47
* Change CellInfo in getBelPinsForCellPin to be const.Keith Rothman2021-02-231-1/+1
* Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-193-36/+5
* Fix sign mismatch.Keith Rothman2021-02-182-2/+2
* Do some spell checking on site_router.ccKeith Rothman2021-02-181-18/+18
* Add some utility methods for site instance access.Keith Rothman2021-02-183-13/+42
* Update README's with latest instructions and features.Keith Rothman2021-02-183-20/+94
* Add utility targets for getting plain text outputs.Keith Rothman2021-02-171-1/+5
* Add IOSTANDARD to ports.Keith Rothman2021-02-171-1/+3
* Emit fixed attributes to output physical netlist.Keith Rothman2021-02-171-8/+19
* Refactor "get only from iterator" to a utility.Keith Rothman2021-02-173-12/+9
* Keep all build artifacts under create_bba/build.Keith Rothman2021-02-172-4/+5
* Change how package pin IO sites are selected.Keith Rothman2021-02-173-16/+52
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