aboutsummaryrefslogtreecommitdiffstats
path: root/generic/arch.h
Commit message (Collapse)AuthorAgeFilesLines
* Add stub cluster API impl for remaining archesgatecat2021-05-061-0/+11
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add "checkPipAvailForNet" to Arch API.Keith Rothman2021-03-221-0/+1
| | | | | | | | This is important for distiguishing valid pseudo pips in the FPGA interchange arch. This also avoids a double or triple lookup of pip->net map. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Split nextpnr.h to allow for linear inclusion.Keith Rothman2021-03-151-3/+12
| | | | | | | | | | | | | | | | | | | "nextpnr.h" is no longer the god header. Important improvements: - Functions in log.h can be used without including BaseCtx/Arch/Context. This means that log_X functions can be called without included "nextpnr.h" - NPNR_ASSERT can be used without including "nextpnr.h" by including "nextpnr_assertions.h". This allows NPNR_ASSERT to be used safely in any header file. - Types defined in "archdefs.h" are now available without including BaseCtx/Arch/Context. This means that utility classes that will be used inside of BaseCtx/Arch/Context can be defined safely in a self-contained header. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Change CellInfo in getBelPinsForCellPin to be const.Keith Rothman2021-02-231-1/+1
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-191-15/+10
| | | | | | | | | | | | | | | | | This replaces the arch-specific DelayInfo structure with new DelayPair (min/max only) and DelayQuad (min/max for both rise and fall) structures that form part of common code. This further reduces the amount of arch-specific code; and also provides useful data structures for timing analysis which will need to delay with pairs/quads of delays as it is improved. While there may be a small performance cost to arches that didn't separate the rise/fall cases (arches that aren't currently separating the min/max cases just need to be fixed...) in DelayInfo, my expectation is that inlining will mean this doesn't make much difference. Signed-off-by: gatecat <gatecat@ds0.me>
* Remove isValidBelForCellgatecat2021-02-161-1/+0
| | | | | | | | | | | | | | | | | This Arch API dates from when we were first working out how to implement placement validity checking, and in practice is little used by the core parts of placer1/HeAP and the Arch implementation involves a lot of duplication with isBelLocationValid. In the short term; placement validity checking is better served by the combination of checkBelAvail and isValidBelForCellType before placement; followed by isBelLocationValid after placement (potentially after moving/swapping multiple cells). Longer term, removing this API makes things a bit cleaner for a new validity checking API. Signed-off-by: gatecat <gatecat@ds0.me>
* generic: Add APIs for controlling cell->bel pin mappinggatecat2021-02-151-2/+5
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Merge pull request #575 from YosysHQ/gatecat/belpin-2gatecat2021-02-151-0/+2
|\ | | | | Support for cell pin to bel pin mappings
| * Add getBelPinsForCellPin to Arch APIgatecat2021-02-101-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | This is a basic implementation, without considering "M of N" arrangements (e.g. for LUT permuation where you only want to route to 1 out of 4/6 sinks) or using a type other than IdString to identify bel pins. But this is also enough to start working out where in nextpnr will break due to removing the 1:1 cell:bel pin cardinality, as a next step. Signed-off-by: gatecat <gatecat@ds0.me>
* | Add getBelHidden and add some missing "override" statements.Keith Rothman2021-02-111-1/+3
|/ | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Use 'T' postfix to disambiguate LHS and RHS of usingD. Shah2021-02-081-21/+21
| | | | | | | Arches might otherwise have range types named ambigiously with the entry in ArchRanges. Signed-off-by: D. Shah <dave@ds0.me>
* Add archArgs and archArgsToId to Arch APID. Shah2021-02-051-2/+3
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* generic: Base upon ArchAPID. Shah2021-02-051-102/+132
| | | | | | | As generic is often picked as our 'odd-one-out' we also use it as an example of an Arch that does not build upon BaseArch. Signed-off-by: D. Shah <dave@ds0.me>
* generic: Fix pin names accidentally being IdStringList not IdStringD. Shah2021-02-051-1/+1
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* Mark IdString and IdStringList single argument constructors explicit.Keith Rothman2021-02-041-5/+5
| | | | | | | | | Single argument constructors will silently convert to that type. This is typically not the right thing to do. For example, the nexus and ice40 arch_pybindings.h files were incorrectly parsing bel name strings, etc. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Post-rebase fixD. Shah2021-02-021-4/+3
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* generic: Use IdStringList for all arch object namesD. Shah2021-02-021-38/+41
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* arch: Add getNameDelimiter API for string listsD. Shah2021-02-021-0/+1
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* Run "make clangformat".Keith Rothman2021-02-021-23/+13
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Rename Partition -> BelBucket.Keith Rothman2021-02-021-9/+9
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Finish implementing new generic APIs.Keith Rothman2021-02-021-3/+15
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add archcheck for partition methods.Keith Rothman2021-02-021-0/+28
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Initial refactoring of placer API.Keith Rothman2021-02-021-0/+3
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Remove wire alias APIDavid Shah2020-10-151-3/+1
| | | | | | It has not actually been implemented in any router for over 2.5 years and causes nothing more than confusion. It can always be added back if it forms part of a future solution; possibly as part of a more general database structure rethink. Signed-off-by: David Shah <dave@ds0.me>
* generic: Implement getRouteBoundingBoxDavid Shah2020-02-031-0/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Allow selection of router algorithmDavid Shah2020-02-031-0/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* generic: Improve error handling when Wire/Pip/Bel is not foundDavid Shah2019-11-271-0/+5
| | | | Signed-off-by: David Shah <dave@ds0.me>
* generic: Router param tweaksDavid Shah2019-04-041-2/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* generic: Cell timing supportDavid Shah2019-04-041-0/+34
| | | | Signed-off-by: David Shah <dave@ds0.me>
* generic: Simple procedural example worksDavid Shah2019-04-021-2/+0
| | | | Signed-off-by: David Shah <dave@ds0.me>
* generic: Add a simple packer for generic SLICEs and IOBsDavid Shah2019-04-021-1/+14
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Add --placer option and refactor placer selectionDavid Shah2019-03-241-0/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge remote-tracking branch 'origin/master' into timingapiEddie Hung2018-11-131-0/+2
|\
| * Add getConflictingWireWire() arch API, streamline getConflictingXY semanticClifford Wolf2018-11-111-1/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Add getConflictingPipWire() arch API, router1 improvementsClifford Wolf2018-11-111-0/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | generic: Update arch to new timing APIDavid Shah2018-11-121-2/+12
|/ | | | Signed-off-by: David Shah <dave@ds0.me>
* Add Arch attrs APIClifford Wolf2018-08-141-0/+10
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add pip locationsClifford Wolf2018-08-091-3/+7
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge branch 'master' of github.com:YosysHQ/nextpnr into constidsClifford Wolf2018-08-081-2/+4
|\
| * Merge pull request #44 from YosysHQ/improve_timing_specDavid Shah2018-08-081-2/+2
| |\ | | | | | | Speed up budget allocator using topographical ordering and update cell timing API
| | * Arch API: Removing Arch::isIOCellDavid Shah2018-08-081-2/+0
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| | * Arch API: New specification for timing port classesDavid Shah2018-08-081-2/+2
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| | * Add Arch::isIOCell() to ecp5 and genericEddie Hung2018-08-061-0/+2
| | |
| | * Modify getBudgetOverride for generic and ecp5 tooEddie Hung2018-08-051-1/+1
| | |
| * | Merge remote-tracking branch 'origin/master' into common_mainMiodrag Milanovic2018-08-081-13/+16
| |\ \ | | | | | | | | | | | | | | | | | | | | # Conflicts: # ecp5/main.cc # ice40/main.cc
| * | | Added project loaderMiodrag Milanovic2018-08-061-0/+2
| | | |
* | | | Get rid of BelType and PortPin in generic archClifford Wolf2018-08-081-10/+4
| |/ / |/| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Modify getBudgetOverride for generic and ecp5 tooEddie Hung2018-08-061-1/+1
| |/ |/|
* | API change: Use CellInfo* and NetInfo* as cell/net handles (generic)Clifford Wolf2018-08-051-12/+15
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* various fixes for generic archMiodrag Milanovic2018-08-021-1/+0
|
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-30 08:38:08 +0000