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cells.cc
Commit message (
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Author
Age
Files
Lines
*
gowin: Add PLL support for the GW1NR-9C chip
YRabbit
2023-01-26
1
-34
/
+23
*
gowin: add a PLL primitive for the GW1NS-4 series
YRabbit
2023-01-18
1
-0
/
+37
*
gowin: use ctx->idf() a bit
YRabbit
2022-11-11
1
-34
/
+14
*
gowin: add initial PLL support
YRabbit
2022-11-10
1
-0
/
+64
*
refactor: Use IdString::in instead of || chains
gatecat
2022-08-10
1
-3
/
+2
*
gowin: Remove incomprehensible names of the muxes
YRabbit
2022-07-19
1
-3
/
+3
*
Merge branch 'master' into shadowram
Pepijn de Vos
2022-07-02
1
-0
/
+3
|
\
|
*
gowin: Add support for long wires
YRabbit
2022-05-27
1
-0
/
+3
*
|
hook up CE maybe
Pepijn de Vos
2022-06-16
1
-0
/
+1
*
|
lutram actually PnRs
Pepijn de Vos
2022-06-06
1
-0
/
+10
*
|
WIP shadowram
Pepijn de Vos
2022-06-05
1
-0
/
+33
|
/
*
Gowin: use global VCC and VSS nets (#956)
Pepijn de Vos
2022-03-19
1
-0
/
+4
*
gowin: Add the Global Set/Reset primitive
YRabbit
2022-03-12
1
-0
/
+2
*
refactor: New member functions to replace design_utils
gatecat
2022-02-18
1
-19
/
+19
*
refactor: Use cell member functions to add ports
gatecat
2022-02-16
1
-20
/
+14
*
refactor: New NetInfo and CellInfo constructors
gatecat
2022-02-16
1
-7
/
+3
*
gowin: Add simplified IO cells processing
YRabbit
2021-12-20
1
-2
/
+10
*
gowin: Replace the zero delays with reasonable values.
YRabbit
2021-10-09
1
-0
/
+2
*
gowin: add support for wide LUTs.
YRabbit
2021-10-07
1
-1
/
+22
*
Fixing old emails and names in copyrights
gatecat
2021-06-12
1
-1
/
+1
*
Using hashlib in arches
gatecat
2021-06-02
1
-1
/
+1
*
clangformat
David Shah
2020-12-30
1
-1
/
+1
*
Gowin target (#542)
Pepijn de Vos
2020-12-30
1
-0
/
+142