| Commit message (Collapse) | Author | Age | Files | Lines |
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For example, clearly distinguish between
GW1N-4
GW1NR-4
GW1NS-4
GW1NSR-4
GW1NSR-4
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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Another simplification of the input regular expression, now
the speed is taken from the base.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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Instead of parsing the partnumber with a regular expression,
a simple table is used. This is done because the structure
of the partnumber changes as new features appear (e.g., ES instead of C6/I5)
This commit does not yet disable the very first regular expression check.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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- Both the mode used by yosys and all Gowin primitive modes are supported.
- The ALU always starts with a zero slice.
- The maximum length of the ALU chain is limited to one line of the chip.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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* A hardwired MUX within each logical cell is used.
* The delay is equal 0.
* No user placement constraints.
* The output route contains dummy PIPs. They are ignored by gowin_pack, but it may be worth removing them.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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Allow the registers of the same type or pairs shown below to be
placed in the same slide:
|--------|--------|
| DFFS | DFFR |
| DFFSE | DFFRE |
| DFFP | DFFC |
| DFFPE | DFFCE |
| DFFNS | DFFNR |
| DFFNSE | DFFNRE |
| DFFNP | DFFNC |
| DFFNPE | DFFNCE |
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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Added support for the INS_LOC instruction in the constraints file
(.CST), which is used to specify object placement.
Expanded treatment of IO_LOC/IO_PORT constraints, which now can
be applied to both ports and IO buffers.
Port constraints have priority.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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Specifying pin placement with this notation (e.g. IOR4B) allows
to use the same constraint file without changes for different
packages and even different families.
The vendor router also understands this notation.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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Add support for IOBUF and TBUF I/O modes.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Pin modes parser
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Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@trabucayre.com>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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"nextpnr.h" is no longer the god header. Important improvements:
- Functions in log.h can be used without including
BaseCtx/Arch/Context. This means that log_X functions can be called
without included "nextpnr.h"
- NPNR_ASSERT can be used without including "nextpnr.h" by including
"nextpnr_assertions.h". This allows NPNR_ASSERT to be used safely in
any header file.
- Types defined in "archdefs.h" are now available without including
BaseCtx/Arch/Context. This means that utility classes that will be
used inside of BaseCtx/Arch/Context can be defined safely in a
self-contained header.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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This replaces the arch-specific DelayInfo structure with new DelayPair
(min/max only) and DelayQuad (min/max for both rise and fall) structures
that form part of common code.
This further reduces the amount of arch-specific code; and also provides
useful data structures for timing analysis which will need to delay
with pairs/quads of delays as it is improved.
While there may be a small performance cost to arches that didn't
separate the rise/fall cases (arches that aren't currently separating
the min/max cases just need to be fixed...) in DelayInfo, my expectation
is that inlining will mean this doesn't make much difference.
Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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Signed-off-by: gatecat <gatecat@ds0.me>
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This Arch API dates from when we were first working out how to
implement placement validity checking, and in practice is little used by
the core parts of placer1/HeAP and the Arch implementation involves a
lot of duplication with isBelLocationValid.
In the short term; placement validity checking is better served by the
combination of checkBelAvail and isValidBelForCellType before placement;
followed by isBelLocationValid after placement (potentially after
moving/swapping multiple cells).
Longer term, removing this API makes things a bit cleaner for a new
validity checking API.
Signed-off-by: gatecat <gatecat@ds0.me>
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This is a basic implementation, without considering "M of N"
arrangements (e.g. for LUT permuation where you only want to route to 1
out of 4/6 sinks) or using a type other than IdString to identify bel
pins.
But this is also enough to start working out where in nextpnr will break
due to removing the 1:1 cell:bel pin cardinality, as a next step.
Signed-off-by: gatecat <gatecat@ds0.me>
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Arches might otherwise have range types named ambigiously with the entry
in ArchRanges.
Signed-off-by: D. Shah <dave@ds0.me>
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Signed-off-by: D. Shah <dave@ds0.me>
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Signed-off-by: D. Shah <dave@ds0.me>
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