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* gowin: fix styleYRabbit2023-04-201-16/+16
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: fix styleYRabbit2023-04-201-1/+1
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: add a common mechanism for placing portsYRabbit2023-04-202-53/+35
| | | | | | | If the port is in a different cell than the primitive, then use the alias mechanism. Considerably compact code for OSC as an example. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Remove inherited code for ODDR(c)YRabbit2023-04-144-153/+40
| | | | | | | Implement ODDR(c) as part of IOLOGIC and remove all old code associated with those primitives. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Fix styleYRabbit2023-04-121-1/+1
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: implement IDES16 and OSER16 primitivesYRabbit2023-04-125-19/+454
| | | | | | | | | These are very cumbersome primitives that take up two cells and consequently 4 IOLOGIC bels. The primitives are implemented for the chips that contain them and are supported by apicula GW1NSR-4C, GW1NR-9 and GW1NR-9C. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Add implementation of IDDR and IDDRC primitivesYRabbit2023-04-062-17/+30
| | | | | | | | Simple deserialization primitives are implemented for all supported boards. Compatible with older apicula bases. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Add support for IDES primitivesYRabbit2023-04-043-16/+159
| | | | | | | | | | | | * placement of IDES4, IVIDEO, IDES8 and IDES10 primitives is supported; * primitives are implemented for the GW1N-1, GW1NZ-1, GW1NSR-4C, GW1NR-9, GW1NR-9C chips; * tricks required for IOLOGIC to work on one side of the -9 and -9C chips are taken into account; Compatible with old apicula bases. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: bugfixYRabbit2023-03-232-2/+3
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Rename questionable portsYRabbit2023-03-233-50/+50
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Change the way errors are processedYRabbit2023-03-231-4/+4
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Add support for OSER primitivesYRabbit2023-03-236-40/+338
| | | | | | | | | | | | | | | | * placement of OSER4, OVIDEO, OSER8 and SER10 primitives is supported; * primitives are implemented for the GW1N-1, GW1NZ-1, GW1NSR-4C, GW1NR-9, GW1NR-9C chips; * the initial support for special HCLK clock wires is implemented to the extent necessary for OSER primitives to function; * output to both regular IO and TLVDS_OBUF is supported; * tricks required for IOLOGIC to work on one side of the -9 and -9C chips are taken into account; * various edits, such as using idf() instead of the local buffer. Compatible with old apicula bases. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* cmake: Make HeAP placer always-enabledgatecat2023-03-171-9/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* gowin: Add bels for new types of oscillatoruis2023-02-062-0/+21
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* gowin: Add PLL support for the GW1NS-2C chipYRabbit2023-01-312-1/+8
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Add PLL support for GW1NR-4 chipsYRabbit2023-01-312-2/+6
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Proper use of the C++ mechanismsYRabbit2023-01-302-10/+8
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Add PLL support for the GW1NR-9 chipYRabbit2023-01-303-46/+56
| | | | | | | | | And also unified the fixing of PLL to bels: the point is that PLL being at a certain location has the possibility to use a direct implicit wire to the clock source, but once we decide to use this direct wire, the PLL can no longer be moved. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Add PLL support for the GW1NR-9C chipYRabbit2023-01-267-104/+125
| | | | | | | | | | | | | | | | | | | | This chip is used in the Tangnano9k board. * all parameters of the rPLL primitive are supported; * all PLL outputs are treated as clock sources and optimized routing is applied to them; * primitive rPLL on different chips has a completely different structure: for example in GW1N-1 it takes two cells, and in GW1NR-9C as many as four, despite this unification was carried out and different chips are processed by the same functions, but this led to the fact that you can not use the PLL chip GW1N-1 with the old apicula bases - will issue a warning and refuse to encode primitive. In other cases compatibility is supported. * Cosmetic change: the usage report shows the rPLL names without any service bels. * I use ctx->idf() on occasion, it's not a total redesign. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: improve error messageYRabbit2023-01-191-1/+2
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: to use the FB network detection functionYRabbit2023-01-191-0/+6
| | | | | | | The chip used in tangnano4k does not have such pins, but we call the function anyway in the expectation of other chips. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: add a PLL primitive for the GW1NS-4 seriesYRabbit2023-01-187-38/+202
| | | | | | | | | | * both instances of the new PLLVR type are supported; * primitive placement is optimized for the use of dedicated PLL clock pins; * all 4 outputs of each primitive can use the clock nets (only 5 lines in total at the same time so far). Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: improve clock wire routingYRabbit2022-12-305-45/+69
| | | | | | | | | | | | | | The dedicated router for clock wires now understands not only the IO pins but also the rPLL outputs as clock sources. This simple router sets an optimal route, so it is now the default router. It can be disabled with the --disable-globals command line flag if desired, but this is not recommended due to possible clock skew. Still for GW1N-4C there is no good router for clock wires as there external quartz resonator is connected via PLL. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: correct the delay calculationYRabbit2022-12-291-5/+16
| | | | | | | And do a full enumeration when searching for a delay because it is not yet clear whether the orderliness of the vector is guaranteed. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: fix build for wasmYRabbit2022-12-213-0/+12
| | | | | | | | A large number of global variables are not suitable for WASM, so completely disable the graphics part where the main array of them is used. For other architectures GUI is still possible. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: not crush on unknown clock tap's sourcesYRabbit2022-12-141-1/+1
| | | | | | As preparation for possible changes to the clock wiring system. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: BUGFIX: Correctly handle resetsYRabbit2022-12-092-13/+14
| | | | | | | | | | When a single primitive occupies several cells, care must be taken when manipulating the parameters of that primitive: when creating cells, each cell must receive a copy of all the parameters and not modify them unnecessarily. That is, if possible, it is better to make all parameter changes before dividing the primitive into cells. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Merge pull request #1059 from YosysHQ/gatecat/validity-errorsmyrtle2022-12-072-2/+2
|\ | | | | Add new option for verbose validity errors, use for ice40
| * api: add explain_invalid option to isBelLocationValidgatecat2022-12-072-2/+2
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Merge pull request #1058 from YosysHQ/gatecat/bounds-refactormyrtle2022-12-072-3/+3
|\| | | | | refactor: rename ArcBounds -> BoundingBox and use this in HeAP
| * refactor: ArcBounds -> BoundingBoxgatecat2022-12-072-3/+3
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | gowin: change the way networks are handledYRabbit2022-12-061-7/+8
| | | | | | | | | | | | | | Until a comprehensive clock router is developed, the order in which private cases are handled is important. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* | gowin: add PLL pins processingYRabbit2022-12-045-10/+133
|/ | | | | | | | | | | Uses the information of the special input pins for the PLL in the current chip. If such pins are involved, no routing is performed and information about the use of implicit wires is passed to the packer. The RESET and RESET_P inputs are now also disabled if they are connected to VSS/VCC. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: add information about pin configurationsYRabbit2022-11-252-4/+22
| | | | | | | Includes information on additional pin functions such as RPLL_C_IN, GCLKC_3, SCLK and others. This allows a decision to be made about special network routing of such pins Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: mark the PLL ports that are not in useYRabbit2022-11-202-0/+16
| | | | | | | Unused ports are deactivated by special fuse combinations, rather than being left dangling in the air. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: add support for a more common chipYRabbit2022-11-121-1/+1
| | | | | | | | The GW1N-1 and GW1NZ-1 have a similar PLL, but the board with the former chip is already very hard to buy, so let's experiment with a more affordable chip. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: use ctx->idf() a bitYRabbit2022-11-112-41/+17
| | | | | | | Replacing snprintf() with ctx->idf() in PLL commit, but not yet a complete overhaul. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: add initial PLL supportYRabbit2022-11-106-1/+227
| | | | | | | | | | | The rPLL primitive for the simplest chip (GW1N-1) in the family is processed. All parameters of the primitive are passed on to gowin_pack, and general-purpose wires are used for routing outputs of the primitive. Compatible with older versions of apicula, but in this case will refuse to place the new primitive. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* run clangformatgatecat2022-10-171-1/+2
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* support windows line endingsLushay Labs2022-10-091-4/+4
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* gowin: BUGFIX. Really memorize the chipYRabbit2022-08-251-0/+2
| | | | | | | When it really needed to distinguish between the chips, this unforgivable error was discovered :) Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* refactor: Use IdString::in instead of || chainsgatecat2022-08-103-6/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* refactor: id(stringf(...)) to new idf(...) helpergatecat2022-08-101-1/+1
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* gowin: fix compilationYRabbit2022-07-191-8/+0
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Remove incomprehensible names of the muxesYRabbit2022-07-197-34/+30
| | | | | | | | | | | | There is no need to multiply item names, it is a rudiment of my very first addition to nextpnr. Fully compatible with older versions of Apicula. Note: the cosmetic changes in lines with RAM are not my initiative, but the result of applying clang-format. Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gowin: Remove unnecessary functionsYRabbit2022-07-052-33/+9
| | | | Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Merge branch 'master' into clock-wipYRabbit2022-07-056-0/+187
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| * use DFF RAM modePepijn de Vos2022-07-021-1/+4
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| * Merge branch 'master' into shadowramPepijn de Vos2022-07-025-15/+310
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| * | hook up CE maybePepijn de Vos2022-06-163-0/+4
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