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* ice40: Use snake case for arch-specific functionsD. Shah2021-02-031-11/+11
| | | | | | | This makes the difference clearer between the general arch API that everyone must implement; and helper functions specific to one arch. Signed-off-by: D. Shah <dave@ds0.me>
* ice40: Implement IdStringList for all arch object namesD. Shah2021-02-021-14/+25
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* arch: Add getNameDelimiter API for string listsD. Shah2021-02-021-0/+1
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* Run "make clangformat".Keith Rothman2021-02-021-18/+14
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Rename Partition -> BelBucket.Keith Rothman2021-02-021-19/+19
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Add Partition APIs to ice40, nexus, gowin archs.Keith Rothman2021-02-021-0/+43
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* Initial refactoring of placer API.Keith Rothman2021-02-021-0/+5
| | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
* cleanup: Spelling fixesD. Shah2021-01-281-1/+1
| | | | Signed-off-by: D. Shah <dave@ds0.me>
* Move RelPtr/RelSlice out of arches into commonD. Shah2021-01-271-42/+1
| | | | | | | The bba approach seems widely used enough that it's reasonable for this to become part of common code. Signed-off-by: D. Shah <dave@ds0.me>
* ice40: Switch from RelPtr to RelSliceD. Shah2021-01-271-40/+51
| | | | | | | | | | This replaces RelPtrs and a separate length field with a Rust-style slice containing both a pointer and a length; with bounds checking always enforced. Thus iterating over these structures is both cleaner and safer. Signed-off-by: D. Shah <dave@ds0.me>
* RelPtr: remove copy constructor and copy assignmentDavid Shah2020-11-131-0/+3
| | | | | | | These operations are meaningless for a data structure that references another structure relative to its location. Signed-off-by: David Shah <dave@ds0.me>
* Remove wire alias APIDavid Shah2020-10-151-9/+0
| | | | | | It has not actually been implemented in any router for over 2.5 years and causes nothing more than confusion. It can always be added back if it forms part of a future solution; possibly as part of a more general database structure rethink. Signed-off-by: David Shah <dave@ds0.me>
* Support rest of partsMiodrag Milanovic2020-07-081-0/+3
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* Adding LP4K as wellMiodrag Milanovic2020-07-081-0/+1
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* Support 4K parts directlyMiodrag Milanovic2020-07-081-0/+1
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* Simplify and improve chipdb embedding/loading.whitequark2020-06-261-14/+3
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* CMake: rewrite chipdb handling from ground up.whitequark2020-06-251-1/+1
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* ice40: Implement getRouteBoundingBox for router2David Shah2020-02-031-0/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Allow selection of router algorithmDavid Shah2020-02-031-0/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Add --placer option and refactor placer selectionDavid Shah2019-03-241-0/+3
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: support u4kSimon Schubert2019-02-231-1/+4
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* Load chipdb from filesystem as optionMiodrag Milanovic2019-02-091-1/+1
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* timing: Path related fixesDavid Shah2019-01-271-1/+4
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: Add helper to know which global network is driven by a SB_GB BelSylvain Munaut2018-11-261-0/+7
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Add GlobalNetowkrInfo in the chip databaseSylvain Munaut2018-11-191-1/+17
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40/arch: Add helper to check if a BEL is LOCKED or notSylvain Munaut2018-11-191-0/+2
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* Merge remote-tracking branch 'origin/master' into timingapiEddie Hung2018-11-131-0/+1
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| * [ice40] getBudgetOverride() to use constrained Z not placed ZEddie Hung2018-11-131-0/+1
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* | Merge remote-tracking branch 'origin/master' into timingapiEddie Hung2018-11-131-17/+37
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| * Merge pull request #107 from YosysHQ/router_improveEddie Hung2018-11-131-17/+37
| |\ | | | | | | Major rewrite of "router1"
| | * clangformatClifford Wolf2018-11-111-4/+1
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * Add getConflictingWireWire() arch API, streamline getConflictingXY semanticClifford Wolf2018-11-111-14/+29
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * Add getConflictingPipWire() arch API, router1 improvementsClifford Wolf2018-11-111-9/+17
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | archapi: Add getDelayFromNS to improve timing algorithm portabilityDavid Shah2018-11-121-0/+6
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | timing: iCE40 Arch API changes for clocking infoDavid Shah2018-11-121-2/+4
|/ / | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* / fix grid dimensions for ice40Miodrag Milanovic2018-10-271-2/+2
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* clangformatDavid Shah2018-09-301-1/+1
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Add iCE40 gfx for span-4 wires between IO tilesClifford Wolf2018-08-191-2/+0
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #47 from YosysHQ/settings_propagateClifford Wolf2018-08-181-2/+0
|\ | | | | Use settings for placer1 and router1
| * Use settings for placer1 and router1Miodrag Milanovic2018-08-091-2/+0
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* | Improve iCE40 gfx for IO tiles and RAM tilesClifford Wolf2018-08-181-0/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add ice40 wire attributes (grid position, segment list)Clifford Wolf2018-08-181-18/+5
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add Arch attrs APIClifford Wolf2018-08-141-0/+18
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge remote-tracking branch 'origin/master' into placer_speedupEddie Hung2018-08-101-1/+11
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| * Add pip locationsClifford Wolf2018-08-091-1/+11
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Rework Arch::logicCellsCompatible() to take pointer + size, allowing use of ↵Eddie Hung2018-08-101-1/+1
|/ | | | std::array
* Merge branch 'master' of github.com:YosysHQ/nextpnr into constidsClifford Wolf2018-08-081-10/+11
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| * Merge pull request #44 from YosysHQ/improve_timing_specDavid Shah2018-08-081-10/+10
| |\ | | | | | | Speed up budget allocator using topographical ordering and update cell timing API
| | * Arch API: Removing Arch::isIOCellDavid Shah2018-08-081-2/+0
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| | * Arch API: New specification for timing port classesDavid Shah2018-08-081-4/+2
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
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