Commit message (Collapse) | Author | Age | Files | Lines | |
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* | ice40: fixes before review | Sergiusz Bazanski | 2018-07-24 | 1 | -6/+6 |
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* | ice40: move PLL->IO from pseudo pip to second uphill bel | Sergiusz Bazanski | 2018-07-24 | 1 | -15/+16 |
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* | ice40: emit list of upbels in chipdb | Sergiusz Bazanski | 2018-07-24 | 1 | -1/+1 |
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* | clang-format | Sergiusz Bazanski | 2018-07-24 | 1 | -14/+21 |
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* | ice40: A slightly nicer way to do this. | Sergiusz Bazanski | 2018-07-24 | 1 | -46/+31 |
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* | ice40: Refactor PLL/LOCK LUT splicing out into Arch:: | Sergiusz Bazanski | 2018-07-24 | 1 | -0/+1 |
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* | ice40: Implement emitting PLLs | Sergiusz Bazanski | 2018-07-24 | 1 | -14/+104 |
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* | clangformat | David Shah | 2018-07-23 | 1 | -2/+3 |
| | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | Move to new API and remove deprecated | Miodrag Milanovic | 2018-07-22 | 1 | -36/+38 |
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* | Rename getWireBelPin to getBelPinWire | Clifford Wolf | 2018-07-22 | 1 | -3/+3 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Added driver and users for nets | Miodrag Milanovic | 2018-07-21 | 1 | -0/+8 |
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* | Map ports to nets | Miodrag Milanovic | 2018-07-21 | 1 | -0/+14 |
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* | create io cells out of asc | Miodrag Milanovic | 2018-07-21 | 1 | -0/+27 |
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* | add cells that are in default state or no configuration | Miodrag Milanovic | 2018-07-21 | 1 | -0/+40 |
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* | Add used cells and attach them to bels | Miodrag Milanovic | 2018-07-21 | 1 | -0/+39 |
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* | Assign proper pips | Miodrag Milanovic | 2018-07-21 | 1 | -9/+27 |
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* | add only missing net | Miodrag Milanovic | 2018-07-21 | 1 | -3/+6 |
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* | fix introduced bug | Miodrag Milanovic | 2018-07-21 | 1 | -0/+2 |
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* | Bind wires to net | Miodrag Milanovic | 2018-07-20 | 1 | -629/+637 |
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* | Few more checks on parameters and error eol | Miodrag Milanovic | 2018-07-20 | 1 | -4/+4 |
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* | Start adding bitstream reading for ice40 | Miodrag Milanovic | 2018-07-20 | 1 | -33/+133 |
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* | ice40: Packer and bitstream gen support for MAC16s | David Shah | 2018-07-19 | 1 | -1/+89 |
| | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | Reducing performance cost of asserts | David Shah | 2018-07-19 | 1 | -1/+1 |
| | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | ice40: Fixes for inverted clocks | David Shah | 2018-07-18 | 1 | -1/+1 |
| | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | ice40: Assign ArchArgs after packing | David Shah | 2018-07-18 | 1 | -2/+3 |
| | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | Revert "Make ice40::Arch thread-safe" | Sergiusz Bazanski | 2018-07-14 | 1 | -5/+5 |
| | | | | This reverts commit 0816f447b768ebe0632f419e9b696714dda4e860. | ||||
* | Revert "Remove legacy access to state via Arch" | Sergiusz Bazanski | 2018-07-14 | 1 | -7/+6 |
| | | | | This reverts commit 18b4b316782035daa259d65d26ea733ca4d16bea. | ||||
* | Remove legacy access to state via Arch | Sergiusz Bazanski | 2018-07-14 | 1 | -6/+7 |
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* | Make ice40::Arch thread-safe | Sergiusz Bazanski | 2018-07-13 | 1 | -5/+5 |
| | | | | | | | | | | | We move all non-chip data to be private and guard them with an R/W mutex. We then modify all calls that access these fields to lock/shared_lock the mutex as required. Profiling the code before and after is an exercise left to the reader :). | ||||
* | Updates from clang-format | Clifford Wolf | 2018-07-12 | 1 | -3/+2 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Add NPNR_ASSERT_FALSE, use in bitstream.cc | David Shah | 2018-07-04 | 1 | -2/+2 |
| | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | refactor: Replace assert with NPNR_ASSERT | David Shah | 2018-07-04 | 1 | -11/+11 |
| | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | Fixed macros and includes for MSVC | Miodrag Milanovic | 2018-07-03 | 1 | -0/+1 |
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* | ice40: UltraPlus SPRAM working | David Shah | 2018-06-29 | 1 | -0/+23 |
| | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | ice40: PLace legaliser produces a design that is at least routable for picosoc | David Shah | 2018-06-28 | 1 | -1/+2 |
| | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | CarryInSet added to bitstream gen, add counter tb | David Shah | 2018-06-26 | 1 | -0/+7 |
| | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | Working on debugging carry packer | David Shah | 2018-06-26 | 1 | -2/+2 |
| | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | nets and cells are unique_ptr's | Miodrag Milanovic | 2018-06-25 | 1 | -17/+17 |
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* | Update from increased clangformat line length | David Shah | 2018-06-23 | 1 | -126/+62 |
| | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | Refactoring bind/unbind API | Clifford Wolf | 2018-06-23 | 1 | -1/+1 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | ice40: Fix UltraPlus quasi-logic-cell bits | David Shah | 2018-06-23 | 1 | -25/+29 |
| | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | Cleanup almost all deprecation warnings | Miodrag Milanovic | 2018-06-23 | 1 | -2/+2 |
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* | ice40: SB_LFOSC support, fabric routing only | David Shah | 2018-06-22 | 1 | -8/+33 |
| | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | ice40: Adding extra cell wires to database; SB_WARMBOOT working | David Shah | 2018-06-22 | 1 | -1/+2 |
| | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | ice40: Add UltraPlus tiles to database | David Shah | 2018-06-22 | 1 | -0/+15 |
| | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | Switched from clifford@clifford.at to clifford@symbioticeda.com for ↵ | Clifford Wolf | 2018-06-22 | 1 | -1/+1 |
| | | | | | | copyright headers Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Fixing 5k bitstream gen and place heuristics | David Shah | 2018-06-22 | 1 | -1/+12 |
| | | | | Signed-off-by: David Shah <davey1576@gmail.com> | ||||
* | Getting rid of old IdString API users, Add ctx to many internal APIs | Clifford Wolf | 2018-06-18 | 1 | -24/+30 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Rename Design to Context, derive from Arch instead of instantiating | Clifford Wolf | 2018-06-18 | 1 | -35/+34 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Rename Chip to Arch and ChipArgs to ArchArgs | Clifford Wolf | 2018-06-18 | 1 | -21/+21 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> |