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* ice40: Add support for SB_I2C and SB_SPISylvain Munaut2019-03-251-0/+22
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: support u4kSimon Schubert2019-02-231-1/+11
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* ice40: Add PCF support for -pullup, -pullup_resistor and -nowarnDavid Shah2018-12-201-2/+15
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ice40: Improve bitstream error handlingDavid Shah2018-12-061-2/+10
| | | | | | Fixes #161 and provides a clearer error for #170 Signed-off-by: David Shah <dave@ds0.me>
* clangformatDavid Shah2018-12-061-1/+1
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: Add support for placing SB_LEDDA_IP block.Daniel Serpell2018-12-011-1/+2
| | | | Signed-off-by: Daniel Serpell <daniel.serpell@gmail.com>
* ice40: Update the way LVDS inputs are handled during bitstream generationSylvain Munaut2018-11-281-48/+48
| | | | | | | | | | | | | | | * Instead of "patching" input_en, we completely separate config for normal and LVDS pair. - For normal pair, nothing changes - For LVDS pairs, the IE/REN bits are always set as if the input buffer are disabled. Then if input_en was set to 1 (i.e. the input is actually for something), then we set the IoCtrl.LVDS bit. - Also for LVDS, if input is used, pullups are forcibly disabled. * When scanning for unused IOs, never process those part of a LVDS pair. They will have been configured by the complement Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Add support for SB_RGBA_DRVSylvain Munaut2018-11-191-0/+5
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Add support for SB_GB_IOSylvain Munaut2018-11-191-0/+1
| | | | | | | | | | During packing we replace them by standard SB_IO cells and create the 'fake' SB_GB that matches that IO site global buffer connection. It's done in a separate pass because we need to make sure the nextpnr iob have been dealt first so we have our final Bel location on the SB_IO. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Add support for PLL global outputs via PADINSylvain Munaut2018-11-191-44/+50
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Introduce the concept of forPadIn SB_GBSylvain Munaut2018-11-191-1/+17
| | | | | | | | | | | | | | Those are cells that are created mainly to handle the various sources a global network can be driven from other than a user net. When the flag is set, this means the global network usually driven by this BEL is in fact driven by something else and so that SB_GB BEL and matching global network can't be used. This is also what gets used to set the extra bits during bitstream generation. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40/bitstream: Handle IoCtrl.IE_ polarity when configuring unused SB_IOSylvain Munaut2018-11-191-2/+7
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40/bitstream: Convert to UNIX line endingsSylvain Munaut2018-11-161-1043/+1043
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Remove unnecessary RAM assertionDavid Shah2018-11-161-1/+0
| | | | | | Fixes #121 Signed-off-by: David Shah <dave@ds0.me>
* ice40: Don't set colbuf bits for 384David Shah2018-11-111-0/+2
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* clangformatDavid Shah2018-09-301-4/+1
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ice40: LVDS input bitstream supportDavid Shah2018-09-241-4/+48
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* do not break if there are no nets loaded from sym sectionMiodrag Milanovic2018-08-181-4/+6
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* Get rid of PortPin and BelType (ice40, generic, docs)Clifford Wolf2018-08-081-17/+17
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* API change: Use CellInfo* and NetInfo* as cell/net handles (common, ice40)Clifford Wolf2018-08-051-24/+24
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* clangformatClifford Wolf2018-08-051-21/+22
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* ice40: Bitstream gen for LUT permutationDavid Shah2018-08-041-8/+78
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ice40: Add bitstream gen for routethru LUTsDavid Shah2018-08-031-9/+58
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ice40: Add HFOSC support, force fabric routing on oscillators for nowDavid Shah2018-08-011-0/+4
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* clangformatSergiusz Bazanski2018-08-011-2/+3
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* clangformatEddie Hung2018-07-251-3/+2
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* ice40: fixes before reviewSergiusz Bazanski2018-07-241-6/+6
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* ice40: move PLL->IO from pseudo pip to second uphill belSergiusz Bazanski2018-07-241-15/+16
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* ice40: emit list of upbels in chipdbSergiusz Bazanski2018-07-241-1/+1
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* clang-formatSergiusz Bazanski2018-07-241-14/+21
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* ice40: A slightly nicer way to do this.Sergiusz Bazanski2018-07-241-46/+31
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* ice40: Refactor PLL/LOCK LUT splicing out into Arch::Sergiusz Bazanski2018-07-241-0/+1
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* ice40: Implement emitting PLLsSergiusz Bazanski2018-07-241-14/+104
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* clangformatDavid Shah2018-07-231-2/+3
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Move to new API and remove deprecatedMiodrag Milanovic2018-07-221-36/+38
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* Rename getWireBelPin to getBelPinWireClifford Wolf2018-07-221-3/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Added driver and users for netsMiodrag Milanovic2018-07-211-0/+8
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* Map ports to netsMiodrag Milanovic2018-07-211-0/+14
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* create io cells out of ascMiodrag Milanovic2018-07-211-0/+27
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* add cells that are in default state or no configurationMiodrag Milanovic2018-07-211-0/+40
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* Add used cells and attach them to belsMiodrag Milanovic2018-07-211-0/+39
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* Assign proper pipsMiodrag Milanovic2018-07-211-9/+27
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* add only missing netMiodrag Milanovic2018-07-211-3/+6
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* fix introduced bugMiodrag Milanovic2018-07-211-0/+2
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* Bind wires to netMiodrag Milanovic2018-07-201-629/+637
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* Few more checks on parameters and error eolMiodrag Milanovic2018-07-201-4/+4
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* Start adding bitstream reading for ice40Miodrag Milanovic2018-07-201-33/+133
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* ice40: Packer and bitstream gen support for MAC16sDavid Shah2018-07-191-1/+89
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Reducing performance cost of assertsDavid Shah2018-07-191-1/+1
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ice40: Fixes for inverted clocksDavid Shah2018-07-181-1/+1
| | | | Signed-off-by: David Shah <davey1576@gmail.com>
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