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* Add info message for promoted global netsClifford Wolf2018-10-031-0/+2
* ice40: Add error for bad PACKAGE_PIN connectionsDavid Shah2018-10-031-2/+13
* clangformatDavid Shah2018-09-301-15/+23
* Merge pull request #79 from YosysHQ/ice40lvdsClifford Wolf2018-09-251-1/+1
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| * ice40: Tristate IO support fixesDavid Shah2018-09-241-1/+1
* | Merge pull request #76 from YosysHQ/plloutglobal_fixClifford Wolf2018-09-251-2/+36
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| * | Added required checks for PLL and fixed messages eolMiodrag Milanovic2018-09-191-3/+31
| * | Add needed PLLOUTGLOBAL ports and mapped it properlyMiodrag Milanovic2018-09-121-0/+6
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* / ice40: Fix carry packer bugDavid Shah2018-09-251-2/+2
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* ice40: make PLL packing more robustSergiusz Bazanski2018-08-191-11/+26
* Get rid of PortPin and BelType (ice40, generic, docs)Clifford Wolf2018-08-081-3/+3
* Fixing constraint placement bugsDavid Shah2018-08-031-2/+3
* Reworking packer and placer to use new generic rel legaliserDavid Shah2018-08-031-0/+3
* ice40: Promote 'logic' globals as well as clock/enable/resetDavid Shah2018-08-031-10/+40
* ice40: Add HFOSC support, force fabric routing on oscillators for nowDavid Shah2018-08-011-1/+14
* clangformatSergiusz Bazanski2018-08-011-6/+6
* clangformatEddie Hung2018-07-251-6/+6
* ice40: check PLL PACKAGEPIN drives only PLL, cosmeticsSergiusz Bazanski2018-07-251-4/+7
* clang-formatSergiusz Bazanski2018-07-251-7/+7
* ice40: support PLL40_*_PAD, fix pass-through LUT for LOCKSergiusz Bazanski2018-07-251-7/+65
* ice40: after reviewSergiusz Bazanski2018-07-241-1/+0
* Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr into q3k/pllSergiusz Bazanski2018-07-241-0/+4
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| * ice40: Remove use of deprecated APIsDavid Shah2018-07-241-2/+3
| * ice40: Trim BRAM constant inputs, reduces routing congestion around BRAMDavid Shah2018-07-241-0/+3
* | ice40: fixes before reviewSergiusz Bazanski2018-07-241-14/+5
* | clang-formatSergiusz Bazanski2018-07-241-51/+53
* | ice40: Move spliceLUT back to pack.ccSergiusz Bazanski2018-07-241-2/+53
* | ice40: Refactor PLL/LOCK LUT splicing out into Arch::Sergiusz Bazanski2018-07-241-74/+3
* | ice40: Emit feed-through LUTs for PLL/LOCKSergiusz Bazanski2018-07-241-1/+158
* | ice40: Fail early on SB_PLL40_*_PAD cellsSergiusz Bazanski2018-07-241-0/+7
* | ice40: Implement emitting PLLsSergiusz Bazanski2018-07-241-0/+32
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* ice40: Trim DSP inputs that are constant where appropriateDavid Shah2018-07-191-0/+4
* ice40: Packer and bitstream gen support for MAC16sDavid Shah2018-07-191-0/+19
* ice40: RenamingDavid Shah2018-07-181-1/+1
* ice40: Fixes for inverted clocksDavid Shah2018-07-181-0/+4
* ice40: Make assignArchArgs a Arch method; call also after legaliserDavid Shah2018-07-181-31/+1
* ice40: Assign ArchArgs after packingDavid Shah2018-07-181-0/+31
* Add ctx->pack() APIClifford Wolf2018-07-131-2/+2
* Fixed macros and includes for MSVCMiodrag Milanovic2018-07-031-0/+1
* ice40: UltraPlus SPRAM workingDavid Shah2018-06-291-4/+18
* ice40: Fix carry packing in some degenerate casesDavid Shah2018-06-291-23/+18
* ice40: Only pack up to one SB_CARRY into a LCDavid Shah2018-06-271-5/+6
* ice40: Fix IO packerDavid Shah2018-06-271-0/+8
* ice40: Carry packer bugfixDavid Shah2018-06-271-19/+16
* ice40: Fixing the carry packer for a larger designDavid Shah2018-06-271-16/+33
* ice40: Fixing packing of CIN constant driversDavid Shah2018-06-261-1/+1
* Carry chains now routableDavid Shah2018-06-261-3/+18
* Working on debugging the carry legaliserDavid Shah2018-06-261-4/+4
* Fixing packing of carry cellsDavid Shah2018-06-261-24/+49
* Working on debugging carry packerDavid Shah2018-06-261-19/+46
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