aboutsummaryrefslogtreecommitdiffstats
path: root/ice40
Commit message (Collapse)AuthorAgeFilesLines
...
* ice40/pack: Make sure we don't use a LOCKED bel when placing PLLSylvain Munaut2018-11-191-0/+2
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40/arch: Add helper to check if a BEL is LOCKED or notSylvain Munaut2018-11-192-0/+21
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40/chipdb: Fix LOCKED keyword support to include all packagesSylvain Munaut2018-11-191-1/+2
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40/bitstream: Handle IoCtrl.IE_ polarity when configuring unused SB_IOSylvain Munaut2018-11-191-2/+7
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40: Add warning if an instanciated SB_IO has its PACKAGE_PIN used elsewhereSylvain Munaut2018-11-161-0/+5
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* ice40/bitstream: Convert to UNIX line endingsSylvain Munaut2018-11-161-1043/+1043
| | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* clangformatDavid Shah2018-11-161-2/+2
| | | | Signed-off-by: David Shah <dave@ds0.me>
* ice40: Remove unnecessary RAM assertionDavid Shah2018-11-161-1/+0
| | | | | | Fixes #121 Signed-off-by: David Shah <dave@ds0.me>
* Merge remote-tracking branch 'origin/master' into timingapiEddie Hung2018-11-132-4/+5
|\
| * [ice40] getBudgetOverride() to use constrained Z not placed ZEddie Hung2018-11-132-4/+5
| |
* | Merge remote-tracking branch 'origin/master' into timingapiEddie Hung2018-11-133-18/+41
|\|
| * Merge pull request #107 from YosysHQ/router_improveEddie Hung2018-11-132-17/+40
| |\ | | | | | | Major rewrite of "router1"
| | * Various router1 fixes, Add BelId/WireId/PipId::operator<()Clifford Wolf2018-11-131-0/+3
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * clangformatClifford Wolf2018-11-111-4/+1
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * Add getConflictingWireWire() arch API, streamline getConflictingXY semanticClifford Wolf2018-11-111-14/+29
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * Add getConflictingPipWire() arch API, router1 improvementsClifford Wolf2018-11-111-9/+17
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Mark getArchOptions as override in derived classesPedro Vanzella2018-11-131-1/+1
| | |
* | | timing: Add support for clock constraintsDavid Shah2018-11-122-0/+12
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | archapi: Add getDelayFromNS to improve timing algorithm portabilityDavid Shah2018-11-121-0/+6
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | timing: Fix handling of clock inputsDavid Shah2018-11-121-2/+2
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | Working on multi-clock analysisDavid Shah2018-11-121-6/+4
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | timing: iCE40 Arch API changes for clocking infoDavid Shah2018-11-123-21/+68
|/ / | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | ice40: Don't set colbuf bits for 384David Shah2018-11-111-0/+2
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | Merge pull request #93 from YosysHQ/gui_changesMiodrag Milanović2018-11-101-2/+2
|\ \ | |/ |/| Gui changes
| * fix grid dimensions for ice40Miodrag Milanovic2018-10-271-2/+2
| |
* | ice40: Fix SPRAM and IO globalsDavid Shah2018-11-041-0/+4
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | ice40: Fix PLL DYNAMICDELAYDavid Shah2018-10-271-1/+2
|/ | | | Signed-off-by: David Shah <davey1576@gmail.com>
* ups, uncommentMiodrag Milanovic2018-10-271-2/+2
|
* Fixed pip graphicsMiodrag Milanovic2018-10-271-4/+4
|
* Merge pull request #88 from YosysHQ/issue72Eddie Hung2018-10-111-6/+13
|\ | | | | Resolve issue #72
| * [ice40] TimingPortClass of LC.O ports without any inputs now TMG_IGNOREEddie Hung2018-09-151-6/+13
| |
* | Add info message for promoted global netsClifford Wolf2018-10-031-0/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | ice40: Add error for bad PACKAGE_PIN connectionsDavid Shah2018-10-031-2/+13
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | Refactor chain finder to its own fileDavid Shah2018-09-301-39/+1
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | clangformatDavid Shah2018-09-308-28/+34
| | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | Merge pull request #79 from YosysHQ/ice40lvdsClifford Wolf2018-09-258-13/+88
|\ \ | | | | | | ice40: Adding LVDS input support
| * | ice40: LVDS input bitstream supportDavid Shah2018-09-241-4/+48
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | ice40: Tristate IO support fixesDavid Shah2018-09-243-6/+10
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | ice40: Validity check for LVDS IODavid Shah2018-09-244-0/+29
| | | | | | | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
| * | ice40: Remove obsolete belType memberDavid Shah2018-09-243-3/+1
| |/ | | | | | | Signed-off-by: David Shah <davey1576@gmail.com>
* | Merge pull request #76 from YosysHQ/plloutglobal_fixClifford Wolf2018-09-252-2/+38
|\ \ | | | | | | Add needed PLLOUTGLOBAL ports and mapped it
| * | Added required checks for PLL and fixed messages eolMiodrag Milanovic2018-09-191-3/+31
| | |
| * | Add needed PLLOUTGLOBAL ports and mapped it properlyMiodrag Milanovic2018-09-122-0/+8
| |/
* / ice40: Fix carry packer bugDavid Shah2018-09-251-2/+2
|/ | | | Signed-off-by: David Shah <davey1576@gmail.com>
* Merge pull request #56 from YosysHQ/q3k/issue-55Serge Bazanski2018-08-192-12/+28
|\ | | | | ice40: make PLL packing more robust
| * ice40: make PLL packing more robustSergiusz Bazanski2018-08-192-12/+28
| |
* | Add more missing iCE40 gfx (LP/HX is complete now)Clifford Wolf2018-08-193-4/+47
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add iCE40 gfx for carry chain pips and LUT cascade pipsClifford Wolf2018-08-191-5/+43
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Fix iCE40 pip gfx for pips on the top edge of a switchboxClifford Wolf2018-08-191-5/+5
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add iCE40 gfx for IO span-4 cornersClifford Wolf2018-08-193-3/+36
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-14 05:14:00 +0000