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| * General reformattingDavid Shah2018-06-173-3/+3
| * ice40: Add symbol output to bitstream generationDavid Shah2018-06-171-6/+8
| * Updating copyrightsDavid Shah2018-06-1711-4/+12
| * Improving the placer outputDavid Shah2018-06-172-1/+4
| * Add 'get or default' functionsDavid Shah2018-06-171-3/+4
| * ice40: Fixing buildDavid Shah2018-06-172-2/+2
| * place: Fix placer validity checksDavid Shah2018-06-162-0/+24
| * ice40: Proper global promotionDavid Shah2018-06-164-24/+83
| * ice40: Promote reset signalDavid Shah2018-06-164-32/+82
* | Move WireInfoPOD into ChipDB binary blobClifford Wolf2018-06-173-39/+61
* | Minor refactoring of BinaryBlobAssembler, fix alignmentsClifford Wolf2018-06-174-84/+145
* | Progress with chipdb refactoringClifford Wolf2018-06-164-23/+39
* | Progress with chipdb refactoringClifford Wolf2018-06-163-42/+37
* | Progress with chipdb refactoringClifford Wolf2018-06-163-33/+175
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* Update clangformatClifford Wolf2018-06-161-1/+1
* Merge remote-tracking branch 'origin/master' into chipdbngClifford Wolf2018-06-168-21/+122
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| * ice40: Fix RAM config in packerDavid Shah2018-06-161-1/+2
| * ice40: Fix BRAM initialisationDavid Shah2018-06-162-4/+4
| * place: Tidying up the SA placerDavid Shah2018-06-161-1/+1
| * ice40: Include RAM init data in bitstreamDavid Shah2018-06-161-0/+40
| * ice40: Fix bitstream generation when parameters are unspecifiedDavid Shah2018-06-161-13/+23
| * ice40: Bitstream generation for RAMDavid Shah2018-06-161-1/+36
| * ice40: Only place IO at valid pinsDavid Shah2018-06-163-3/+14
| * experiment: Simple heuristic-based placerDavid Shah2018-06-164-6/+10
* | Some refactoring of Chip API (prep for chipdb refactoring)Clifford Wolf2018-06-163-25/+47
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* ice40: Another arch_place fixDavid Shah2018-06-141-1/+1
* ice40: General fixesDavid Shah2018-06-142-11/+21
* ice40: Read cells in arachne placement scriptDavid Shah2018-06-141-1/+1
* ice40: Importer for placed ice40 designs from arachneDavid Shah2018-06-143-0/+35
* Add route-ripup routing loopClifford Wolf2018-06-142-7/+13
* Refactor position/delay estimation APIClifford Wolf2018-06-143-34/+17
* Drastically reduce number of linker symbols in chipdbClifford Wolf2018-06-131-18/+40
* ice40: Rename ICESTORM_RAM pinsDavid Shah2018-06-132-3/+56
* Add picorv32_top module with fewer IO pinsClifford Wolf2018-06-132-1/+32
* Add missing iCE40 global buffer belsClifford Wolf2018-06-131-0/+18
* Add test PicoRV32 build scriptClifford Wolf2018-06-132-0/+7
* Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnrClifford Wolf2018-06-132-3/+38
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| * ice40: Pack RAMsDavid Shah2018-06-133-8/+46
* | Add A*-like optimizations to routerClifford Wolf2018-06-135-9/+28
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* ice40: Promote one clock to a global bufferDavid Shah2018-06-133-1/+61
* Add hierarchy to bel/wire/pip namesClifford Wolf2018-06-133-17/+28
* Fixing implementation of constantsDavid Shah2018-06-133-8/+52
* ice40: Update examples to use packer/pcfDavid Shah2018-06-1310-398/+37
* Update chip Graphics APIClifford Wolf2018-06-132-18/+24
* Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnrClifford Wolf2018-06-1311-242/+306
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| * ice40: Add a PCF parserDavid Shah2018-06-137-171/+131
| * ice40: Add package selectionDavid Shah2018-06-133-3/+25
| * ice40: Add package pins to databaseDavid Shah2018-06-132-3/+52
| * Simple IO buffer insertion, enable packer by defaultDavid Shah2018-06-134-33/+65
| * Remove IO buffers when fed by SB_IODavid Shah2018-06-133-1/+63
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