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* ice40: support u4kSimon Schubert2019-02-2313-13/+57
* ice40: Fix timing class of 'padin' GB outputsDavid Shah2019-02-201-1/+1
* Merge branch 'master' into mmaped_chipdbMiodrag Milanović2019-02-121-1/+8
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| * ice40: PLLs can't conflict with themselvesDavid Shah2019-02-091-0/+2
| * ice40: Don't create PLLOUT_B buffer for single-output PLL variantsDavid Shah2019-02-091-1/+6
* | Fix according to comments on PRMiodrag Milanovic2019-02-101-1/+1
* | Load chipdb from filesystem as optionMiodrag Milanovic2019-02-093-83/+114
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* Merge pull request #220 from YosysHQ/coi3Eddie Hung2019-01-291-6/+9
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| * [ice40] Refactor Arch::getBudgetOverride()Eddie Hung2019-01-291-29/+9
| * ice40: Add budget override for CO->I3 pathDavid Shah2019-01-271-0/+23
* | timing: Path related fixesDavid Shah2019-01-272-6/+33
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* Merge pull request #211 from smunaut/ice40_ram_attrsDavid Shah2019-01-211-0/+4
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| * ice40/pack: Copy attributes to packed RAM cellsSylvain Munaut2019-01-191-0/+4
* | ice40: Add error message if a selected site is not Global Buffer capableSylvain Munaut2019-01-181-0/+4
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* ice40: Add timing data for all IO modesDavid Shah2019-01-072-3/+67
* ice40: Improve handling of unconstrained IODavid Shah2018-12-263-3/+23
* ice40: Add PCF support for -pullup, -pullup_resistor and -nowarnDavid Shah2018-12-202-4/+45
* ice40: Fix LOCK feedthrough insertion with carry or >8 LUTsDavid Shah2018-12-201-4/+10
* ci: Add attosoc smoketest for ice40David Shah2018-12-088-0/+3185
* Merge pull request #163 from daveshah1/timing_optDavid Shah2018-12-073-2/+17
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| * timing_opt: Reduce iterations to 30, tidy up loggingDavid Shah2018-12-061-2/+1
| * timing_opt: Improve heuristicsDavid Shah2018-12-061-1/+1
| * timing_opt: Make an optional pass controlled by command lineDavid Shah2018-12-062-3/+11
| * clangformatDavid Shah2018-12-061-3/+4
| * timing_opt: Debugging and integrationDavid Shah2018-12-061-1/+8
* | ice40: Report error for unsupported PLL FEEDBACK_PATH valuesDavid Shah2018-12-061-7/+11
* | ice40: Improve bitstream error handlingDavid Shah2018-12-061-2/+10
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* clangformatDavid Shah2018-12-062-2/+3
* ice40: Put debug logging behind ctx->debugDavid Shah2018-12-061-3/+5
* ice40: Fix carry chain splittingDavid Shah2018-12-051-1/+1
* ice40: Don't split carry chain in simple feed-out casesDavid Shah2018-12-041-7/+50
* ice40: Include I3 connectivity in chainDavid Shah2018-12-041-23/+25
* ice40: add reset global promotion threshold.whitequark2018-12-041-1/+3
* ice40: Add support for placing SB_LEDDA_IP block.Daniel Serpell2018-12-015-1/+26
* ice40: Add a warning for unconstrained IODavid Shah2018-11-291-6/+5
* Improve reporting of unknown cell typesDavid Shah2018-11-291-1/+1
* Merge pull request #157 from whitequark/fanout-threshDavid Shah2018-11-291-1/+1
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| * ice40: raise CE global promotion threshold.whitequark2018-11-291-1/+1
* | ice40: print fanout of nets promoted to globals.whitequark2018-11-281-7/+11
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* Merge pull request #155 from smunaut/issue_151David Shah2018-11-281-48/+48
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| * ice40: Update the way LVDS inputs are handled during bitstream generationSylvain Munaut2018-11-281-48/+48
* | ice40: Try to be helpful and suggest using PAD PLL instead of CORESylvain Munaut2018-11-281-2/+14
* | ice40: Revamp the whole PLL placement/validity check logicSylvain Munaut2018-11-281-72/+200
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* ice40: Finer-grained control of global promotionDavid Shah2018-11-272-3/+14
* ice40: During global promotion, only promote if this will actually fit !Sylvain Munaut2018-11-261-6/+32
* ice40: Add helper to know which global network is driven by a SB_GB BelSylvain Munaut2018-11-262-2/+8
* ice40: Improve PCF error handlingDavid Shah2018-11-261-3/+9
* Merge branch 'master' of github.com:YosysHQ/nextpnrDavid Shah2018-11-261-0/+2
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| * ice40: Fix disconnection of PACKAGEPIN for PAD PLLsDavid Shah2018-11-241-0/+2
* | python: Fixes to get net wires map workingDavid Shah2018-11-221-2/+24
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