aboutsummaryrefslogtreecommitdiffstats
path: root/machxo2
Commit message (Expand)AuthorAgeFilesLines
* viaduct: Add support for GUIsgatecat2023-04-112-11/+9
* Add ramaining PIO tilesMiodrag Milanovic2023-03-201-4/+11
* Use unified io location dataMiodrag Milanovic2023-03-201-12/+2
* Use TRELLIS primitivesMiodrag Milanovic2023-03-208-40/+39
* Use RelSlice, make more in line with ecp5 archMiodrag Milanovic2023-03-204-146/+113
* cmake: Make HeAP placer always-enabledgatecat2023-03-172-11/+3
* clangformatgatecat2023-03-174-24/+21
* Fix out of tree builds and place h in generatedMiodrag Milanovic2023-03-163-3/+3
* Let top tiles be on topMiodrag Milanovic2023-03-161-3/+3
* Enable wires and add dummy wire type for nowMiodrag Milanovic2023-03-164-7/+32
* Basic GUI part selectionMiodrag Milanovic2023-03-162-3/+3
* Fix examplesMiodrag Milanovic2023-03-165-6/+6
* Extend chipdb with metadataMiodrag Milanovic2023-03-1610-202/+189
* add new field handling in chip config formatMiodrag Milanovic2023-03-162-0/+4
* Add simple BEL graphicsMiodrag Milanovic2023-03-165-1/+245
* Expand list of possible devicesMiodrag Milanovic2023-03-162-4/+29
* machxo2: Fix Python bindings for pip iteratorsLofty2023-02-131-2/+2
* Add missing <set> includesgatecat2023-01-202-0/+3
* api: add explain_invalid option to isBelLocationValidgatecat2022-12-072-2/+2
* refactor: ArcBounds -> BoundingBoxgatecat2022-12-072-3/+3
* Use CMake's Python3 rather than PythonInterp in subdirsAdam Sampson2022-08-211-2/+2
* refactor: id(stringf(...)) to new idf(...) helpergatecat2022-08-101-4/+4
* Switch to potentially-sparse net users arraygatecat2022-02-271-1/+1
* refactor: New member functions to replace design_utilsgatecat2022-02-182-10/+10
* refactor: Use constids instead of id("..")gatecat2022-02-167-64/+81
* refactor: Use cell member functions to add portsgatecat2022-02-161-72/+59
* refactor: New NetInfo and CellInfo constructorsgatecat2022-02-162-16/+9
* archapi: Use arbitrary rather than actual placement in predictDelaygatecat2021-12-192-7/+8
* clangformat.William D. Jones2021-12-162-9/+12
* machxo2: Remove no-iobs option. It was always enabled and should remain an im...William D. Jones2021-12-166-8/+5
* machxo2: Remove -noiopad option when generating miters for post-pnr verificat...William D. Jones2021-12-161-1/+2
* machxo2: Add packing logic to forbid designs lacking FACADE_IO top-level ports.William D. Jones2021-12-161-0/+46
* machxo2: Correct which PIO wires get adjusted when writing text bitstream. Ad...William D. Jones2021-12-161-9/+26
* machxo2: Fix packing for directly-connected DFFs.William D. Jones2021-07-013-9/+28
* machxo2: Add VHDL primitives, demo, and script.William D. Jones2021-07-014-0/+81
* machxo2: Add a special case for pips whose config bits are in multipleWilliam D. Jones2021-07-011-0/+12
* machxo2: Hardcode a rule for emitting U_/D_ or G_ prefixes in ASCII output.William D. Jones2021-07-011-2/+17
* machxo2: Set Pip and Wire delays to reasonable fake values mirroringWilliam D. Jones2021-07-011-2/+2
* Fixing old emails and names in copyrightsgatecat2021-06-1213-15/+15
* Remove redundant code after hashlib movegatecat2021-06-021-43/+0
* Use hashlib in most remaining codegatecat2021-06-021-2/+2
* Using hashlib in archesgatecat2021-06-024-9/+8
* Use hashlib for core netlist structuresgatecat2021-06-023-17/+19
* Add hash() member functionsgatecat2021-06-021-0/+5
* Add stub cluster API impl for remaining archesgatecat2021-05-061-1/+3
* Add same fix as in issue #373Miodrag Milanovic2021-04-081-0/+4
* Split nextpnr.h to allow for linear inclusion.Keith Rothman2021-03-152-7/+18
* Fix compiler warnings introduced by -Wextragatecat2021-02-253-15/+1
* Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-192-36/+3
* Remove isValidBelForCellgatecat2021-02-163-12/+1
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-14 16:16:22 +0000