aboutsummaryrefslogtreecommitdiffstats
path: root/machxo2
Commit message (Collapse)AuthorAgeFilesLines
...
* machxo2: Misc tidying upgatecat2021-02-122-8/+4
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* machxo2: Python bindings and stub GUIgatecat2021-02-125-6/+188
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* machxo2: Use snake_case for non-ArchAPI functionsgatecat2021-02-124-63/+63
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* machxo2: Use IdStringLists in earnestgatecat2021-02-122-76/+70
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* machxo2: Update with Arch API changesgatecat2021-02-127-464/+115
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* machxo2: Prepare README.md for first PR.William D. Jones2021-02-121-4/+36
|
* machxo2: Add prefix parameter to simtest.sh. Remove show command fromWilliam D. Jones2021-02-123-40/+43
| | | | simtest.sh. Update README.md.
* machxo2: Add prefix parameter to simple.sh. Update README.md.William D. Jones2021-02-122-14/+14
|
* machxo2: Fill in more about mitertest.sh in README.md and clean up a bit.William D. Jones2021-02-121-4/+27
|
* machxo2: Add two new examples: blinky_ext and aforementioned UART.William D. Jones2021-02-123-0/+238
|
* machxo2: auto-top does not work for smt miter either.William D. Jones2021-02-121-1/+1
|
* machxo2: Fix unhelpful comment in mitertest.sh.William D. Jones2021-02-121-1/+0
|
* machxo2: Verilog examples using OSCH cannot be simulated in mitertest.sh. ↵William D. Jones2021-02-121-3/+7
| | | | Remove show from mitertest.sh.
* machxo2: Add prefix parameter to mitertest.sh. All Verilog files top modules ↵William D. Jones2021-02-123-37/+37
| | | | named "top".
* machxo2: Add prefix paramter to demo.sh.William D. Jones2021-02-124-22/+37
|
* Add demo with RGB LEDmtnrbq2021-02-122-0/+43
|
* machxo2: Fix packing when FF is driven by a constant; UART test core working ↵William D. Jones2021-02-122-1/+3
| | | | on silicon, fails post-synth sim.
* machxo2: Add packing logic to handle FFs fed with constant value; UART test ↵William D. Jones2021-02-123-5/+39
| | | | core routes.
* machxo2: Add additional packing phase to pack remaining FFs.William D. Jones2021-02-121-0/+38
|
* machxo2: Don't write out config bits for cells without location info.William D. Jones2021-02-121-1/+2
|
* machxo2: Special-case left and right I/O wire names in ASCII generation.William D. Jones2021-02-121-1/+35
|
* machxo2: Add quickstart README.md.William D. Jones2021-02-121-0/+73
|
* machxo2: Fail CMake configuration is BUILD_PYTHON is ON (not supported for now).William D. Jones2021-02-121-0/+3
|
* machxo2: Fix REGMODE identifier (per slice, not per-FF).William D. Jones2021-02-122-5/+2
|
* machxo2: Add demo.sh TinyFPGA Ax example.William D. Jones2021-02-124-1/+50
|
* machxo2: clang format.William D. Jones2021-02-124-29/+34
|
* machxo2: Fix reversed interpretation of REG_SD config bits.William D. Jones2021-02-121-6/+0
|
* machxo2: Add bitstream generation for OSCH.William D. Jones2021-02-121-0/+4
|
* machxo2: Add basic bitstream generation for PIC tiles and I/O.William D. Jones2021-02-121-0/+26
|
* machxo2: Add REGMODE to bitstream output.William D. Jones2021-02-121-0/+1
|
* machxo2: Checkpoint commit for slice bitstream generation.William D. Jones2021-02-123-1/+121
|
* machxo2: Write out pips to bitstream.William D. Jones2021-02-123-0/+83
|
* machxo2: Emit empty bitstream file.William D. Jones2021-02-121-0/+37
|
* machxo2: Add/fix copyright banners.William D. Jones2021-02-128-5/+12
|
* machxo2: Add stub bitstream writer plus support files.William D. Jones2021-02-125-2/+559
|
* machxo2: Tweak A-star parameters for acceptable performance.William D. Jones2021-02-122-3/+26
|
* machxo2: Fix getWireName.William D. Jones2021-02-121-1/+1
|
* machxo2: Fix typos where absolute positions were treated as relative.William D. Jones2021-02-121-6/+6
|
* machxo2: Finish implementing Wire API functions. nextpnr segfaults on ↵William D. Jones2021-02-122-12/+43
| | | | example with constraints.
* machxo2: Finish implementing Pip API functions.William D. Jones2021-02-122-27/+67
|
* machxo2: Implement 4 more Wire/Pip API functions.William D. Jones2021-02-122-32/+94
|
* machxo2: Add stub getAttrs API functions.William D. Jones2021-02-122-13/+21
|
* machxo2: Implement getByName/getName for Wires and Pips.William D. Jones2021-02-122-13/+94
|
* machxo2: Convert facade_import to use pybind API from pytrellis.William D. Jones2021-02-121-9/+7
|
* machxo2: Use attrmvcp in yosys to implement LOC constraint and only check ↵William D. Jones2021-02-121-37/+22
| | | | for LOC on FACADE_IO.
* machxo2: Detect LOC attributes during packing to implement rudimentary user ↵William D. Jones2021-02-123-0/+61
| | | | constraints.
* machxo2: clang format.William D. Jones2021-02-125-74/+32
|
* machxo2: Import remaining iterators from ECP5.William D. Jones2021-02-121-0/+154
|
* machxo2: Implement WireId/PipId, complete Bel part of API.William D. Jones2021-02-123-2/+72
|
* machxo2: Implement all of Bel API except getBelPinWire.William D. Jones2021-02-122-12/+79
|
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-06 19:26:02 +0000