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* mistral: Tidying upgatecat2021-05-151-1/+1
* mistral: Workaround for weird SCLR issuegatecat2021-05-151-0/+7
* mistral: Fix ENA and ACLR bitstream generationgatecat2021-05-151-0/+6
* mistral: Compensate for EF_SEL mirroring in validity checkgatecat2021-05-151-2/+2
* mistral: Fix EF_SEL and BTO_DISgatecat2021-05-151-1/+2
* mistral: Debugging flipflopsgatecat2021-05-151-3/+4
* mistral: First pass at FF and CLKBUF bitgengatecat2021-05-151-8/+13
* mistral: Account for TD input count limitgatecat2021-05-151-3/+87
* mistral: Debugging carry chain issuesgatecat2021-05-151-13/+16
* mistral: Adding FF control set reservationgatecat2021-05-151-51/+104
* mistral: Carry fixesgatecat2021-05-151-2/+14
* mistral: Carry debugginggatecat2021-05-151-39/+6
* mistral: Write arith mode to bitstream (not yet functional)gatecat2021-05-151-2/+15
* mistral: First pass at carry packinggatecat2021-05-151-4/+38
* mistral: FF validity checking fixesgatecat2021-05-151-7/+13
* mistral: Write LUT initsgatecat2021-05-151-1/+35
* mistral: Some preps for generating bitstreamsgatecat2021-05-151-28/+27
* mistral: Adding a function for computing ALM LUT masksgatecat2021-05-151-0/+88
* mistral: Working on FF validity checkinggatecat2021-05-151-1/+116
* mistral: Working on ALM input assignmentgatecat2021-05-151-1/+116
* mistral: Add stub pack/place/route functionsgatecat2021-05-151-0/+27
* mistral: Renamed arch from cyclonevgatecat2021-05-151-0/+399
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