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* clangformatgatecat2021-08-261-3/+3
* mistral: Permute MLAB init bits correctlygatecat2021-08-241-0/+22
* mistral: Use MLABs as if they're LABs (for now)Lofty2021-08-174-50/+63
* mistral: Include mistral generated files in include dirsgatecat2021-08-151-1/+1
* mistral: Fix pip binding checkgatecat2021-08-141-4/+11
* Fixing old emails and names in copyrightsgatecat2021-06-122-2/+2
* mistral: Remove mistral root argumentgatecat2021-06-043-7/+1
* mistral: Build libmistral as a cmake subdirgatecat2021-06-041-4/+3
* Remove redundant code after hashlib movegatecat2021-06-021-29/+2
* Use hashlib in most remaining codegatecat2021-06-021-2/+2
* Using hashlib in archesgatecat2021-06-025-20/+19
* Use hashlib for core netlist structuresgatecat2021-06-024-25/+25
* Add hash() member functionsgatecat2021-06-021-0/+4
* mistral: Fix nextpnr build with LLVMgatecat2021-06-023-4/+4
* mistral: Make RBF compression optionalgatecat2021-05-302-1/+9
* mistral: add getChipNameLofty2021-05-151-1/+1
* mistral: Add MISTRAL_CLKBUF cell typegatecat2021-05-155-1/+15
* mistral: Tidying upgatecat2021-05-1510-10/+10
* mistral: Make router2 the defaultgatecat2021-05-151-1/+1
* mistral: Speed up bel binding and checkinggatecat2021-05-151-4/+18
* mistral: Workaround for weird SCLR issuegatecat2021-05-151-0/+7
* mistral: Fix ENA and ACLR bitstream generationgatecat2021-05-154-4/+11
* mistral: Disable global buffers that are currently brokengatecat2021-05-151-0/+2
* mistral: Compensate for EF_SEL mirroring in validity checkgatecat2021-05-151-2/+2
* mistral: Fix EF_SEL and BTO_DISgatecat2021-05-152-4/+5
* mistral: PKREG bits appear to be mirrored within a half?gatecat2021-05-151-2/+3
* mistral: Debugging flipflopsgatecat2021-05-151-3/+4
* mistral: Trim SDATA if SLOAD is lowgatecat2021-05-151-0/+9
* mistral: FF&CLKBUF fixes, part 1gatecat2021-05-152-1/+10
* mistral: First pass at FF and CLKBUF bitgengatecat2021-05-152-18/+115
* mistral: Account for TD input count limitgatecat2021-05-154-9/+128
* msitral: Fix pip iterator Python bindingsgatecat2021-05-151-2/+2
* mistral: Implement PIP locations, toogatecat2021-05-151-1/+1
* mistral: Implement bounding boxes for router2gatecat2021-05-152-1/+15
* mistral: Debugging carry chain issuesgatecat2021-05-152-13/+34
* mistral: Adding FF control set reservationgatecat2021-05-153-58/+148
* mistral: Carry fixesgatecat2021-05-152-3/+16
* mistral: Carry debugginggatecat2021-05-153-41/+11
* mistral: Write arith mode to bitstream (not yet functional)gatecat2021-05-152-2/+18
* mistral: First pass at carry packinggatecat2021-05-154-8/+82
* mistral: FF validity checking fixesgatecat2021-05-151-7/+13
* mistral: Fix constant trimminggatecat2021-05-152-1/+2
* mistral: Write LUT initsgatecat2021-05-152-1/+72
* mistral: Add some IO configurationgatecat2021-05-151-0/+30
* mistral: Setting some more boilerplate bitsgatecat2021-05-153-1/+118
* mistral: Add stub RBF generationgatecat2021-05-154-9/+108
* mistral: Rename clock buffer primitivegatecat2021-05-152-2/+3
* mistral: Python and GUI stubgatecat2021-05-152-0/+212
* mistral: Implement some misc. thingsgatecat2021-05-154-10/+78
* mistral: Some preps for generating bitstreamsgatecat2021-05-154-28/+131
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 18:43:12 +0000