aboutsummaryrefslogtreecommitdiffstats
path: root/nexus/arch.h
Commit message (Expand)AuthorAgeFilesLines
* Split nextpnr.h to allow for linear inclusion.Keith Rothman2021-03-151-6/+9
* nexus: Add pin definitions for DPHYgatecat2021-03-081-0/+1
* nexus: Fix global handling for LIFCL-17gatecat2021-03-031-1/+1
* nexus: Fix getPipDelay returning negative after refactorgatecat2021-02-231-1/+1
* Replace DelayInfo with DelayPair/DelayQuadgatecat2021-02-191-26/+11
* Remove isValidBelForCellgatecat2021-02-161-5/+0
* Add getBelHidden and add some missing "override" statements.Keith Rothman2021-02-111-1/+1
* Add BaseArchRanges for default ArchRanges typesgatecat2021-02-091-16/+1
* Merge pull request #568 from YosysHQ/dave/arch-overridegatecat2021-02-081-257/+102
|\
| * Use 'T' postfix to disambiguate LHS and RHS of usingD. Shah2021-02-081-21/+21
| * Add archArgs and archArgsToId to Arch APID. Shah2021-02-051-2/+3
| * nexus: Switch to BaseArchD. Shah2021-02-051-255/+99
* | Use RelSlice::ssize instead of cast-to-int throughoutD. Shah2021-02-081-10/+10
|/
* Mark IdString and IdStringList single argument constructors explicit.Keith Rothman2021-02-041-2/+2
* nexus: Implement IdStringList for all arch object namesD. Shah2021-02-021-22/+21
* arch: Add getNameDelimiter API for string listsD. Shah2021-02-021-0/+1
* Run "make clangformat".Keith Rothman2021-02-021-18/+14
* Rename Partition -> BelBucket.Keith Rothman2021-02-021-19/+19
* Add Partition APIs to ice40, nexus, gowin archs.Keith Rothman2021-02-021-0/+43
* Initial refactoring of placer API.Keith Rothman2021-02-021-0/+5
* Seperate PipRange types in pybindings_shared.Keith Rothman2021-02-011-1/+0
* cleanup: Spelling fixesD. Shah2021-01-281-1/+1
* Move RelPtr/RelSlice out of arches into commonD. Shah2021-01-271-39/+1
* nexus: Switch from RelPtr to RelSliceD. Shah2021-01-271-85/+77
* nexus: Fix LRAM pin typesDavid Shah2020-12-071-8/+9
* nexus: Add support for initialised LRAMDavid Shah2020-12-071-3/+4
* nexus: Add basic LRAM support (no init)David Shah2020-12-021-1/+1
* nexus: Fix db integrity checkDavid Shah2020-11-301-1/+1
* nexus: Add post-place LUTFF optimisationDavid Shah2020-11-301-13/+10
* nexus: Preliminary integration of DSP timing dataDavid Shah2020-11-301-0/+4
* nexus: Fix slow routing around DSPsDavid Shah2020-11-301-0/+4
* nexus: Fix validity checking when DSPs are usedDavid Shah2020-11-301-2/+9
* timing: Add a few more cell typesDavid Shah2020-11-301-0/+9
* nexus: Swap sort order to make some lookups easierDavid Shah2020-11-301-1/+1
* nexus: Add cell delay lookupDavid Shah2020-11-301-0/+6
* nexus: Lookup speed grade and pip delaysDavid Shah2020-11-301-1/+10
* nexus: Add timing structures to BBADavid Shah2020-11-301-1/+49
* nexus: Use dedicated Vcc routing for OXIDE_COMB pinsDavid Shah2020-11-301-0/+2
* nexus: Basic support for differential IO typesDavid Shah2020-11-301-0/+31
* nexus: EBR fixesDavid Shah2020-11-301-0/+1
* nexus: Add a simple global routing passDavid Shah2020-11-301-0/+4
* nexus: Generate FASM files that can be used standaloneDavid Shah2020-11-301-1/+1
* nexus: Build and embed chipdb automaticallyDavid Shah2020-11-301-1/+0
* nexus: Add constant/inversion packingDavid Shah2020-11-301-5/+7
* nexus: More pin styles and FASM pinmux genDavid Shah2020-11-301-12/+18
* nexus: Refactor cell pin style dbDavid Shah2020-11-301-1/+4
* nexus: Tidy up FASM backendDavid Shah2020-11-301-1/+1
* nexus: Add IO packingDavid Shah2020-11-301-3/+4
* nexus: Initial PDC parser integrationDavid Shah2020-11-301-1/+1
* nexus: Lookup of package and IO pinsDavid Shah2020-11-301-0/+11
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 18:29:05 +0000